From 3fff6023602822531efdae30bc8ebf862967f1ef Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Mon, 25 Jul 2022 17:55:39 +0200 Subject: Initial Commit --- VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v | 39 +++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v (limited to 'VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v') diff --git a/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v new file mode 100644 index 0000000..7058c11 --- /dev/null +++ b/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps + +module toplevel( + input CLK, + input BUT1, + input BUT2, + output LED1, + output LED2 + ); + + assign LED1 = io_gpioA_write[0]; + assign LED2 = io_gpioA_write[7]; + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire io_mainClk; + + // Use PLL to downclock external clock. + toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK), + .PLLOUTCORE(io_mainClk), + .PLLOUTGLOBAL(), + .RESET(1'b1)); + + Murax murax ( + .io_asyncReset(1'b0), + .io_mainClk (io_mainClk), + .io_jtag_tck(1'b0), + .io_jtag_tdi(1'b0), + .io_jtag_tdo(), + .io_jtag_tms(1'b0), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(), + .io_uart_rxd(0'b0) + ); + +endmodule -- cgit v1.2.3