From 3fff6023602822531efdae30bc8ebf862967f1ef Mon Sep 17 00:00:00 2001
From: Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de>
Date: Mon, 25 Jul 2022 17:55:39 +0200
Subject: Initial Commit

---
 .../src/main/scala/vexriscv/demo/GenSmallest.scala | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 VexRiscv/src/main/scala/vexriscv/demo/GenSmallest.scala

(limited to 'VexRiscv/src/main/scala/vexriscv/demo/GenSmallest.scala')

diff --git a/VexRiscv/src/main/scala/vexriscv/demo/GenSmallest.scala b/VexRiscv/src/main/scala/vexriscv/demo/GenSmallest.scala
new file mode 100644
index 0000000..9813ccf
--- /dev/null
+++ b/VexRiscv/src/main/scala/vexriscv/demo/GenSmallest.scala
@@ -0,0 +1,59 @@
+package vexriscv.demo
+
+import vexriscv.plugin._
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
+import spinal.core._
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenSmallest extends App{
+  def cpu() = new VexRiscv(
+    config = VexRiscvConfig(
+      plugins = List(
+        new IBusSimplePlugin(
+          resetVector = 0x80000000l,
+          cmdForkOnSecondStage = false,
+          cmdForkPersistence = false,
+          prediction = NONE,
+          catchAccessFault = false,
+          compressedGen = false
+        ),
+        new DBusSimplePlugin(
+          catchAddressMisaligned = false,
+          catchAccessFault = false
+        ),
+        new CsrPlugin(CsrPluginConfig.smallest),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = false
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = plugin.SYNC,
+          zeroBoot = false
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = false
+        ),
+        new LightShifterPlugin,
+        new HazardSimplePlugin(
+          bypassExecute           = false,
+          bypassMemory            = false,
+          bypassWriteBack         = false,
+          bypassWriteBackBuffer   = false,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new BranchPlugin(
+          earlyBranch = false,
+          catchAddressMisaligned = false
+        ),
+        new YamlPlugin("cpu0.yaml")
+      )
+    )
+  )
+
+  SpinalVerilog(cpu())
+}
-- 
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