From 3fff6023602822531efdae30bc8ebf862967f1ef Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Mon, 25 Jul 2022 17:55:39 +0200 Subject: Initial Commit --- .../cpp/custom/simd_add/build/custom_simd_add.asm | 63 ++++++++++++++++++ .../cpp/custom/simd_add/build/custom_simd_add.elf | Bin 0 -> 4676 bytes .../cpp/custom/simd_add/build/custom_simd_add.hex | 14 ++++ .../cpp/custom/simd_add/build/custom_simd_add.map | 30 +++++++++ .../cpp/custom/simd_add/build/custom_simd_add.v | 14 ++++ VexRiscv/src/test/cpp/custom/simd_add/makefile | 73 +++++++++++++++++++++ VexRiscv/src/test/cpp/custom/simd_add/src/crt.S | 72 ++++++++++++++++++++ VexRiscv/src/test/cpp/custom/simd_add/src/ld | 15 +++++ 8 files changed, 281 insertions(+) create mode 100644 VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.asm create mode 100755 VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.elf create mode 100644 VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.hex create mode 100644 VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.map create mode 100755 VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.v create mode 100644 VexRiscv/src/test/cpp/custom/simd_add/makefile create mode 100644 VexRiscv/src/test/cpp/custom/simd_add/src/crt.S create mode 100644 VexRiscv/src/test/cpp/custom/simd_add/src/ld (limited to 'VexRiscv/src/test/cpp/custom/simd_add') diff --git a/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.asm b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.asm new file mode 100644 index 0000000..f993948 --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.asm @@ -0,0 +1,63 @@ + +build/custom_simd_add.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +00000000 <_start>: + 0: 00100e13 li t3,1 + 4: 060000b3 0x60000b3 + 8: 08009c63 bnez ra,a0 + c: 00200e13 li t3,2 + 10: 00000093 li ra,0 + 14: 00000113 li sp,0 + 18: 062080b3 0x62080b3 + 1c: 08009263 bnez ra,a0 + 20: 00300e13 li t3,3 + 24: 010200b7 lui ra,0x1020 + 28: 30408093 addi ra,ra,772 # 1020304 + 2c: 00000113 li sp,0 + 30: 062081b3 0x62081b3 + 34: 06119663 bne gp,ra,a0 + 38: 00400e13 li t3,4 + 3c: 03061237 lui tp,0x3061 + 40: 90c20213 addi tp,tp,-1780 # 306090c + 44: 010200b7 lui ra,0x1020 + 48: 30408093 addi ra,ra,772 # 1020304 + 4c: 02040137 lui sp,0x2040 + 50: 60810113 addi sp,sp,1544 # 2040608 + 54: 062081b3 0x62081b3 + 58: 04419463 bne gp,tp,a0 + 5c: 00500e13 li t3,5 + 60: ff000237 lui tp,0xff000 + 64: 10220213 addi tp,tp,258 # ff000102 + 68: fff00093 li ra,-1 + 6c: 00010137 lui sp,0x10 + 70: 20310113 addi sp,sp,515 # 10203 + 74: 062081b3 0x62081b3 + 78: 02419463 bne gp,tp,a0 + 7c: 00600e13 li t3,6 + 80: 00600293 li t0,6 + 84: 00100093 li ra,1 + 88: 00200113 li sp,2 + 8c: 00300193 li gp,3 + 90: 062080b3 0x62080b3 + 94: 063080b3 0x63080b3 + 98: 00509463 bne ra,t0,a0 + 9c: 0100006f j ac + +000000a0 : + a0: f0100137 lui sp,0xf0100 + a4: f2410113 addi sp,sp,-220 # f00fff24 + a8: 01c12023 sw t3,0(sp) + +000000ac : + ac: f0100137 lui sp,0xf0100 + b0: f2010113 addi sp,sp,-224 # f00fff20 + b4: 00012023 sw zero,0(sp) + b8: 00000013 nop + bc: 00000013 nop + c0: 00000013 nop + c4: 00000013 nop + c8: 00000013 nop + cc: 00000013 nop diff --git a/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.elf b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.elf new file mode 100755 index 0000000..889f618 Binary files /dev/null and b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.elf differ diff --git a/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.hex b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.hex new file mode 100644 index 0000000..91ef7e3 --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.hex @@ -0,0 +1,14 @@ +:10000000130E1000B3000006639C0008130E2000BE +:100010009300000013010000B380200663920008E3 +:10002000130E3000B700020193804030130100002E +:10003000B381200663961106130E400037120603A3 +:100040001302C290B70002019380403037010402CE +:1000500013018160B381200663944104130E5000A4 +:10006000370200FF130222109300F0FF3701010056 +:1000700013013120B381200663944102130E600006 +:1000800093026000930010001301200093013000E0 +:10009000B3802006B3803006639450006F000001E7 +:1000A000370110F0130141F22320C101370110F094 +:1000B000130101F2232001001300000013000000CF +:1000C00013000000130000001300000013000000E4 +:00000001FF diff --git a/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.map b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.map new file mode 100644 index 0000000..0f47c3f --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.map @@ -0,0 +1,30 @@ + +Memory Configuration + +Name Origin Length Attributes +onChipRam 0x0000000000000000 0x0000000000002000 w !xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD build/src/crt.o +LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a +START GROUP +LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a +LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a +END GROUP +LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a + 0x0000000000000000 . = 0x0 + +.crt_section 0x0000000000000000 0xd0 + 0x0000000000000000 . = ALIGN (0x4) + *crt.o(.text) + .text 0x0000000000000000 0xd0 build/src/crt.o + 0x0000000000000000 _start +OUTPUT(build/custom_simd_add.elf elf32-littleriscv) + +.data 0x00000000000000d0 0x0 + .data 0x00000000000000d0 0x0 build/src/crt.o + +.bss 0x00000000000000d0 0x0 + .bss 0x00000000000000d0 0x0 build/src/crt.o diff --git a/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.v b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.v new file mode 100755 index 0000000..07cf05d --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/build/custom_simd_add.v @@ -0,0 +1,14 @@ +@00000000 +13 0E 10 00 B3 00 00 06 63 9C 00 08 13 0E 20 00 +93 00 00 00 13 01 00 00 B3 80 20 06 63 92 00 08 +13 0E 30 00 B7 00 02 01 93 80 40 30 13 01 00 00 +B3 81 20 06 63 96 11 06 13 0E 40 00 37 12 06 03 +13 02 C2 90 B7 00 02 01 93 80 40 30 37 01 04 02 +13 01 81 60 B3 81 20 06 63 94 41 04 13 0E 50 00 +37 02 00 FF 13 02 22 10 93 00 F0 FF 37 01 01 00 +13 01 31 20 B3 81 20 06 63 94 41 02 13 0E 60 00 +93 02 60 00 93 00 10 00 13 01 20 00 93 01 30 00 +B3 80 20 06 B3 80 30 06 63 94 50 00 6F 00 00 01 +37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0 +13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 diff --git a/VexRiscv/src/test/cpp/custom/simd_add/makefile b/VexRiscv/src/test/cpp/custom/simd_add/makefile new file mode 100644 index 0000000..49c9179 --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/makefile @@ -0,0 +1,73 @@ +PROJ_NAME=custom_simd_add + + +RISCV_PATH=/opt/riscv/ +CFLAGS += -march=rv32i -mabi=ilp32 +RISCV_NAME = riscv64-unknown-elf +RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy +RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump +RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/ +RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc +LDSCRIPT=src/ld + + +SRCS = $(wildcard src/*.c) \ + $(wildcard src/*.cpp) \ + $(wildcard src/*.S) + + +CFLAGS += -static +LDFLAGS += -e_start -T $(LDSCRIPT) -nostartfiles -Wl,-Map,$(OBJDIR)/$(PROJ_NAME).map -Wl,--print-memory-usage +OBJDIR = build +OBJS := $(SRCS) +OBJS := $(OBJS:.c=.o) +OBJS := $(OBJS:.cpp=.o) +OBJS := $(OBJS:.S=.o) +OBJS := $(addprefix $(OBJDIR)/,$(OBJS)) + + + +all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v + @echo "done" + +$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR) + $(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS) + +%.hex: %.elf + $(RISCV_OBJCOPY) -O ihex $^ $@ + +%.bin: %.elf + $(RISCV_OBJCOPY) -O binary $^ $@ + +%.v: %.elf + $(RISCV_OBJCOPY) -O verilog $^ $@ + +%.asm: %.elf + $(RISCV_OBJDUMP) -S -d $^ > $@ + +$(OBJDIR)/%.o: %.c + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ + +$(OBJDIR)/%.o: %.cpp + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ + +$(OBJDIR)/%.o: %.S + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1 + +$(OBJDIR): + mkdir -p $@ + +clean: + rm -f $(OBJDIR)/$(PROJ_NAME).elf + rm -f $(OBJDIR)/$(PROJ_NAME).hex + rm -f $(OBJDIR)/$(PROJ_NAME).map + rm -f $(OBJDIR)/$(PROJ_NAME).v + rm -f $(OBJDIR)/$(PROJ_NAME).asm + find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm + +.SECONDARY: $(OBJS) + + diff --git a/VexRiscv/src/test/cpp/custom/simd_add/src/crt.S b/VexRiscv/src/test/cpp/custom/simd_add/src/crt.S new file mode 100644 index 0000000..99fa3d3 --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/src/crt.S @@ -0,0 +1,72 @@ +.globl _start +_start: + +#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \ +.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0)) + +#define SIMD_ADD(_rd, _rs1, _rs2 ) \ +r_type_insn(0b0000011, _rs2, _rs1, 0b000, _rd, 0b0110011) + +//Test 1 + li x28, 1 + SIMD_ADD(1, 0, 0) + bne x1, x0, fail + +//Test 2 + li x28, 2 + li x1, 0x00000000 + li x2, 0x00000000 + SIMD_ADD(1, 1, 2) + bne x1, x0, fail + +//Test 3 + li x28, 3 + li x1, 0x01020304 + li x2, 0x00000000 + SIMD_ADD(3, 1, 2) + bne x3, x1, fail + +//Test 4 + li x28, 4 + li x4, 0x0306090C + li x1, 0x01020304 + li x2, 0x02040608 + SIMD_ADD(3, 1, 2) + bne x3, x4, fail + +//Test 5 + li x28, 5 + li x4, 0xFF000102 + li x1, 0xFFFFFFFF + li x2, 0x00010203 + SIMD_ADD(3, 1, 2) + bne x3, x4, fail + +//Test 5 + li x28, 6 + li x5, 0x00000006 + li x1, 0x00000001 + li x2, 0x00000002 + li x3, 0x00000003 + SIMD_ADD(1, 1, 2) + SIMD_ADD(1, 1, 3) + bne x1, x5, fail + + j pass + +fail: //x28 => error code + li x2, 0xF00FFF24 + sw x28, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + + + nop + nop + nop + nop + nop + nop diff --git a/VexRiscv/src/test/cpp/custom/simd_add/src/ld b/VexRiscv/src/test/cpp/custom/simd_add/src/ld new file mode 100644 index 0000000..3a4f112 --- /dev/null +++ b/VexRiscv/src/test/cpp/custom/simd_add/src/ld @@ -0,0 +1,15 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 8K +} + +SECTIONS +{ + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} -- cgit v1.2.3