beckmanf/dtlab.git/sim/makefile, branch master Unnamed repository; edit this file 'description' to name the repository. sim/makefile: added synth step to sim 2024-05-15T04:43:58+00:00 Friedrich Beckmann friedrich.beckmann@hs-augsburg.de 2024-05-15T04:43:58+00:00 8c6f69e2fead5f85b8098bca6c1c4606676a880e The --synth step finds std_ulogic violations with several drivers 
The --synth step finds std_ulogic violations with
several drivers
sim: make the output of the make command more verbose 2024-04-28T11:13:53+00:00 Friedrich Beckmann friedrich.beckmann@hs-augsburg.de 2024-04-28T11:13:53+00:00 ee8d484d8531e425a06f23519fc09bbf2e1acf4e Hans dumped all ghdl output to a logfile to have a short output on the terminal. I prefer to have a more verbose output in case of errors. In addition I fixed a problem when an error occurs during elaboration as the .ghw file is produced also when ghdl exits with an error. Now make will reproduce the error on each call. 
Hans dumped all ghdl output to a logfile to have a short output
on the terminal. I prefer to have a more verbose output in case of
errors. In addition I fixed a problem when an error occurs during
elaboration as the .ghw file is produced also when ghdl exits with
an error. Now make will reproduce the error on each call.
add top_shift and simulation 2024-03-07T11:26:41+00:00 Friedrich Beckmann friedrich.beckmann@hs-augsburg.de 2024-03-07T11:26:41+00:00 e96efbe9496c8f9718869791fa30e444f42ffb38