add top_uart

1 files changed, 37 insertions, 0 deletions

diff --git a/src/top_uart.vhd b/src/top_uart.vhd
new file mode 100644
index 0000000..4cc6c01
--- /dev/null
+++ b/src/top_uart.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top_uart is 
+port ( SW       : in  std_ulogic_vector(9 downto 0);
+       KEY      : in  std_ulogic_vector(3 downto 0);
+       CLOCK_50 : in  std_ulogic;
+       UART_RXD : in  std_ulogic;
+       UART_TXD : out std_ulogic;
+       EXP      : out std_ulogic_vector(7 downto 0);
+       LEDG     : out std_ulogic_vector(3 downto 0);
+       LEDR     : out std_ulogic_vector(9 downto 0));
+end entity;
+
+architecture rtl of top_uart is
+  signal clk     : std_ulogic;
+  signal rst_n   : std_ulogic;
+  signal en, txd : std_ulogic;
+begin
+  -- Assign the inputs to signals with reasonable names
+  clk <= CLOCK_50;
+  rst_n <= KEY(0);
+
+  txd <= '0';
+  en <= '0';
+
+  -- Set the outputs;
+  EXP(7 downto 4) <= "0000";
+  EXP(3 downto 0) <= (3 => txd,
+          2 => en,
+          1 => rst_n,
+          0 => clk);
+  UART_TXD <= txd;
+  LEDR <= SW;
+  LEDG <= KEY;
+
+end architecture rtl;
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