uart rx solutionsolutions

1 files changed, 16 insertions, 3 deletions

diff --git a/src/top_uart.vhd b/src/top_uart.vhd
index d53f06d..abe1e96 100644
--- a/src/top_uart.vhd
+++ b/src/top_uart.vhd
@@ -17,6 +17,7 @@ architecture rtl of top_uart is
   signal rst_n   : std_ulogic;
   signal en, txd : std_ulogic;
   signal start   : std_ulogic;
+  signal dv : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
@@ -48,14 +49,26 @@ begin
       tx_o    => txd
   );
 
+  uart_rx_inst: entity work.uart_rx
+   port map(
+      clk         => clk,
+      rst_n       => rst_n,
+      uart_rxd_i  => UART_RXD,
+      rxd_o       => LEDR(7 downto 0),
+      dv_o        => dv
+  );
+
   -- Set the outputs;
-  EXP(7 downto 4) <= "0000";
-  EXP(3 downto 0) <= (3 => txd,
+  EXP(7 downto 6) <= "00";
+  EXP(5 downto 0) <= (
+          5 => dv,
+          4 => UART_RXD,
+          3 => txd,
           2 => en,
           1 => rst_n,
           0 => clk);
   UART_TXD <= txd;
-  LEDR <= SW;
+  LEDR(9 downto 8) <= "00";
   LEDG <= KEY;
 
 end architecture rtl;
\ No newline at end of file