top_uart solutions

1 files changed, 5 insertions, 1 deletions

diff --git a/src/uart_tx_shift.vhd b/src/uart_tx_shift.vhd
index b81fe78..f5724f6 100644
--- a/src/uart_tx_shift.vhd
+++ b/src/uart_tx_shift.vhd
@@ -12,7 +12,11 @@ entity uart_tx_shift is
 end entity;
 
 architecture rtl of uart_tx_shift is
+  signal sr, srn : std_ulogic_vector(8 downto 0);
 begin
-
+  sr <= (others => '1') when rst_n = '0' else srn when rising_edge(clk);
+  srn <= d_i & '0' when start_i = '1' else
+         '1' & sr(8 downto 1) when en_i = '1' else sr;
+  tx_o <= sr(0);
 end architecture rtl;