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-rw-r--r--src/cnt1sec.vhd6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cnt1sec.vhd b/src/cnt1sec.vhd
index a722ff9..14fad68 100644
--- a/src/cnt1sec.vhd
+++ b/src/cnt1sec.vhd
@@ -10,7 +10,11 @@ entity cnt1sec is
end entity;
architecture rtl of cnt1sec is
+ signal cnt, ncnt : unsigned(25 downto 0);
begin
-
+ cnt <= (others => '0') when rst_n = '0' else ncnt when rising_edge(clk);
+ ncnt <= to_unsigned(0,cnt'length) when cnt = 4 else
+ cnt + 1;
+ en_o <= '1' when cnt = 0 else '0';
end architecture rtl;