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Diffstat (limited to 'src/top_shift.vhd')
| -rw-r--r-- | src/top_shift.vhd | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/top_shift.vhd b/src/top_shift.vhd new file mode 100644 index 0000000..f6036bc --- /dev/null +++ b/src/top_shift.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top_shift is +port ( SW : in std_ulogic_vector(9 downto 0); + KEY : in std_ulogic_vector(3 downto 0); + CLOCK_50 : in std_ulogic; + EXP : out std_ulogic_vector(7 downto 0); + LEDG : out std_ulogic_vector(3 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end entity; + +architecture rtl of top_shift is + signal clk : std_ulogic; + signal rst_n : std_ulogic; + signal x : std_ulogic; + signal sr, srnext : std_ulogic_vector(0 to 1); + signal en : std_ulogic; +begin + -- Assign the inputs to signals with reasonable names + clk <= CLOCK_50; + rst_n <= KEY(0); + x <= KEY(1); + + ------------------------- + -- The edge detector + ------------------------- + -- Designpattern Register + -- Create a register with two flipflops with low active + -- asynchronous reset. + -- D-Input is connected to srnext + -- Q Outputs are connected to sr + sr <= "00" when rst_n = '0' else srnext when rising_edge(clk); + + -- Implement the shift register function with next state logic + srnext(0) <= x; + srnext(1) <= sr(0); + + -- Compute the output function from the shift register content + en <= sr(0) xor sr(1); + + -------------------------- + -- New code here + -------------------------- + + -- Set the outputs; + EXP <= (7 downto 4 => '0', + 3 => en, + 2 => x, + 1 => rst_n, + 0 => clk); + LEDR <= SW; + LEDG <= KEY; + +end architecture rtl;
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