aboutsummaryrefslogtreecommitdiff
path: root/src/top_shift.vhd
diff options
context:
space:
mode:
Diffstat (limited to 'src/top_shift.vhd')
-rw-r--r--src/top_shift.vhd19
1 files changed, 15 insertions, 4 deletions
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
index 5b9db02..96691e0 100644
--- a/src/top_shift.vhd
+++ b/src/top_shift.vhd
@@ -15,6 +15,8 @@ architecture rtl of top_shift is
signal rst_n : std_ulogic;
signal x : std_ulogic;
signal en : std_ulogic;
+ signal en_edge : std_ulogic;
+ signal led : std_ulogic_vector(9 downto 0);
begin
-- Assign the inputs to signals with reasonable names
clk <= CLOCK_50;
@@ -26,15 +28,24 @@ begin
clk => clk,
rst_n => rst_n,
x_i => x,
- edge_o => en);
+ edge_o => en_edge);
+
+ ringcnt_inst: entity work.ringcnt
+ port map(
+ clk => clk,
+ rst_n => rst_n,
+ en_i => en,
+ y_o => led);
+
+ en <= '1' when SW(0) = '1' else en_edge;
-- Set the outputs;
- EXP <= (7 downto 4 => '0',
+ EXP <= (7 downto 4 => led(9 downto 6),
3 => en,
2 => x,
1 => rst_n,
0 => clk);
- LEDR <= SW;
+ LEDR <= led;
LEDG <= KEY;
-end architecture rtl; \ No newline at end of file
+end architecture rtl;