diff options
Diffstat (limited to 'src/top_shift.vhd')
| -rw-r--r-- | src/top_shift.vhd | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/src/top_shift.vhd b/src/top_shift.vhd index d0c6f44..5b9db02 100644 --- a/src/top_shift.vhd +++ b/src/top_shift.vhd @@ -14,7 +14,6 @@ architecture rtl of top_shift is signal clk : std_ulogic; signal rst_n : std_ulogic; signal x : std_ulogic; - signal sr, srnext : std_ulogic_vector(1 downto 0); signal en : std_ulogic; begin -- Assign the inputs to signals with reasonable names @@ -22,22 +21,12 @@ begin rst_n <= KEY(0); x <= KEY(1); - ------------------------- - -- The edge detector - ------------------------- - -- Designpattern Register - -- Create a register with two flipflops with low active - -- asynchronous reset. - -- D-Input is connected to srnext - -- Q Outputs are connected to sr - sr <= "00" when rst_n = '0' else srnext when rising_edge(clk); - - -- Implement the shift register function with next state logic - srnext(1) <= x; - srnext(0) <= sr(1); - - -- Compute the output function from the shift register content - en <= sr(1) xor sr(0); + edge_inst: entity work.edge + port map( + clk => clk, + rst_n => rst_n, + x_i => x, + edge_o => en); -- Set the outputs; EXP <= (7 downto 4 => '0', |