From 8c6f69e2fead5f85b8098bca6c1c4606676a880e Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Wed, 15 May 2024 06:43:58 +0200 Subject: sim/makefile: added synth step to sim The --synth step finds std_ulogic violations with several drivers --- sim/makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/makefile b/sim/makefile index 2d78311..7404189 100644 --- a/sim/makefile +++ b/sim/makefile @@ -33,6 +33,7 @@ wave : t_$(PROJECT).ghw #==== SIMULATION ====# t_$(PROJECT).ghw : .compile.done + $(GHDL_CMD) --synth --out=none $(GHDL_OPTIONS) $(PROJECT) # If ghdl exits with an error code, remove the .ghw file $(GHDL_CMD) -r $(GHDL_OPTIONS) t_$(PROJECT) --wave=t_$(PROJECT).ghw \ || (rm -f t_$(PROJECT).ghw; exit 1) @@ -58,7 +59,7 @@ synthcheck : .compile.done @echo "---- $@" >> $(LOG_FILE) 2>&1 @$(TIME_STAMP_LOG_FILE) @echo "Synthesis Check ..." >> $(LOG_FILE) 2>&1 - @$(GHDL_CMD) --synth --out=none $(GHDL_OPTIONS) $(PROJECT) 2>&1 | tee -a $(LOG_FILE) + $(GHDL_CMD) --synth --out=none $(GHDL_OPTIONS) $(PROJECT) 2>&1 | tee -a $(LOG_FILE) @$(TIME_STAMP) > .synth.done warnings: $(LOG_FILE) -- cgit v1.2.3