From 70f4b9e97d88ade1dc262d930edd27ef97de58ae Mon Sep 17 00:00:00 2001
From: Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de>
Date: Sun, 28 Apr 2024 17:49:04 +0200
Subject: moved edgedetection to edge module, 6 clock design

---
 src/edge.vhd | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'src/edge.vhd')

diff --git a/src/edge.vhd b/src/edge.vhd
index 23dba70..d510660 100644
--- a/src/edge.vhd
+++ b/src/edge.vhd
@@ -10,7 +10,11 @@ entity edge is
 end entity;
 
 architecture rtl of edge is
+  signal sr, srnext : std_ulogic_vector(5 downto 0);
 begin
-
+  sr <= "000000" when rst_n = '0' else srnext when rising_edge(clk);
+  srnext(5) <= x_i;
+  srnext(4 downto 0) <= sr(5 downto 1);
+  edge_o <= '1' when sr = "111000" or sr = "000111" else '0';
 end architecture rtl;
 
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