From e96efbe9496c8f9718869791fa30e444f42ffb38 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Thu, 7 Mar 2024 12:26:41 +0100 Subject: add top_shift and simulation --- src/t_top_shift.vhd | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 src/t_top_shift.vhd (limited to 'src/t_top_shift.vhd') diff --git a/src/t_top_shift.vhd b/src/t_top_shift.vhd new file mode 100644 index 0000000..996b6d1 --- /dev/null +++ b/src/t_top_shift.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity t_top_shift is +end entity; + +architecture beh of t_top_shift is + + signal sim_clk : std_ulogic; + signal sim_rst_n : std_ulogic; + signal sim_x : std_ulogic; + signal sim_y : std_ulogic; + + signal sim_sw : std_ulogic_vector(9 downto 0); + signal sim_key : std_ulogic_vector(3 downto 0); + signal sim_ledr : std_ulogic_vector(9 downto 0); + signal sim_ledg : std_ulogic_vector(3 downto 0); + signal sim_exp : std_ulogic_vector(7 downto 0); + + signal simstop : boolean := false; + +begin + + -- Stimuli clock generator + clk_p : process + begin + sim_clk <= '0'; + wait for 10 ns; + sim_clk <= '1'; + wait for 10 ns; + if simstop then + wait; + end if; + end process; + + -- Stimuli reset generator + sim_rst_n <= '0', '1' after 55 ns; + + -- Stimuli key push + sim_x <= '0', '1' after 135 ns, '0' after 195 ns; + + -- Simulation stopper + simstop <= true after 300 ns; + + -- Device under test instantiation + dut : entity work.top_shift + port map( + SW => sim_sw, + KEY => sim_key, + CLOCK_50 => sim_clk, + EXP => sim_exp, + LEDG => sim_ledg, + LEDR => sim_ledr + ); + + -- Connect stimuli to input signals + sim_key(0) <= sim_rst_n; + sim_key(1) <= sim_x; + sim_key(3 downto 2) <= "00"; + sim_sw <= "1010000101"; + + -- Check the expansion port y output + sim_y <= sim_exp(3); + +end architecture beh; \ No newline at end of file -- cgit v1.2.3