From 3467ff482ed8a58b525c992329df639872e52fdc Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Fri, 8 Mar 2024 10:14:47 +0100 Subject: add top_hex --- src/top_hex.vhd | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 src/top_hex.vhd (limited to 'src/top_hex.vhd') diff --git a/src/top_hex.vhd b/src/top_hex.vhd new file mode 100644 index 0000000..cfe2d33 --- /dev/null +++ b/src/top_hex.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top_hex is +port ( SW : in std_ulogic_vector(9 downto 0); + HEX0 : out std_ulogic_vector(6 downto 0); + HEX1 : out std_ulogic_vector(6 downto 0); + HEX2 : out std_ulogic_vector(6 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end entity; + +architecture rtl of top_hex is +begin + +LEDR <= SW; + +bin2seg_i0: entity work.bin2seg + port map( + bin_i => SW(3 downto 0), + seg_o => HEX0 +); + +HEX1 <= "1111111"; +HEX2 <= "1111111"; + +end architecture rtl; -- cgit v1.2.3