From aa054291a7f4eaf136d228d851354bd879fd8fe1 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Tue, 28 May 2024 12:20:02 +0200 Subject: add uart_rx_edge --- src/uart_rx_edge.vhd | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 src/uart_rx_edge.vhd (limited to 'src/uart_rx_edge.vhd') diff --git a/src/uart_rx_edge.vhd b/src/uart_rx_edge.vhd new file mode 100644 index 0000000..9a85f92 --- /dev/null +++ b/src/uart_rx_edge.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity uart_rx_edge is + port ( + clk : in std_ulogic; + rst_n : in std_ulogic; + rxd_i : in std_ulogic; + rxd_o : out std_ulogic; + edge_o : out std_ulogic); +end entity; + +architecture rtl of uart_rx_edge is + signal sr, nsr : std_ulogic_vector(1 downto 0); +begin + sr <= "00" when rst_n = '0' else nsr when rising_edge(clk); + nsr <= rxd_i & sr(1); + rxd_o <= sr(0); + edge_o <= '1' when sr = "01" else '0'; +end architecture rtl; + -- cgit v1.2.3