From 2caa12d7f849d5bb5aebed5f306f2def408ae8e3 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Mon, 27 May 2024 17:32:24 +0200 Subject: uart rx solution --- src/uart_rx_shift.vhd | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/uart_rx_shift.vhd') diff --git a/src/uart_rx_shift.vhd b/src/uart_rx_shift.vhd index 273931c..30a8403 100644 --- a/src/uart_rx_shift.vhd +++ b/src/uart_rx_shift.vhd @@ -11,6 +11,10 @@ entity uart_rx_shift is end entity; architecture rtl of uart_rx_shift is + signal sr, nsr : std_ulogic_vector(7 downto 0); begin + sr <= "00000000" when rst_n = '0' else nsr when rising_edge(clk); + nsr <= ser_i & sr(7 downto 1) when shift_i = '1' else sr; + d_o <= sr; end architecture rtl; -- cgit v1.2.3