From e367cceeadc06e7007e1ff9757dfd568184dae02 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Mon, 11 Mar 2024 19:53:14 +0100 Subject: top_hex: add adder --- src/top_hex.vhd | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/top_hex.vhd b/src/top_hex.vhd index cfe2d33..af0da77 100644 --- a/src/top_hex.vhd +++ b/src/top_hex.vhd @@ -1,26 +1,41 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; entity top_hex is port ( SW : in std_ulogic_vector(9 downto 0); HEX0 : out std_ulogic_vector(6 downto 0); HEX1 : out std_ulogic_vector(6 downto 0); HEX2 : out std_ulogic_vector(6 downto 0); + HEX3 : out std_ulogic_vector(6 downto 0); LEDR : out std_ulogic_vector(9 downto 0)); end entity; architecture rtl of top_hex is + signal sa : signed(4 downto 0); + signal sb : signed(4 downto 0); + signal sum : signed(4 downto 0); begin LEDR <= SW; +sa <= signed(SW(4 downto 0)); +sb <= signed(SW(9 downto 5)); +sum <= sa + sb; + +bin2seg_i1: entity work.bin2seg + port map( + bin_i => "000" & std_ulogic(sum(4)), + seg_o => HEX1 +); + bin2seg_i0: entity work.bin2seg port map( - bin_i => SW(3 downto 0), + bin_i => std_ulogic_vector(sum(3 downto 0)), seg_o => HEX0 ); -HEX1 <= "1111111"; -HEX2 <= "1111111"; +HEX2 <= "1111111" when sa > -1 else "0000000"; +HEX3 <= "1111111"; end architecture rtl; -- cgit v1.2.3