library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity baudcnt is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    start_i : in std_ulogic;
    en_o    : out std_ulogic);
end entity;

architecture rtl of baudcnt is
  signal cnt, ncnt : unsigned(9 downto 0);
begin
  cnt <= (others => '0') when rst_n = '0' else
         ncnt when rising_edge(clk);
  ncnt <= to_unsigned(0, cnt'length) when start_i = '1' or cnt = 2 else
          cnt + 1;
  en_o <= '1' when cnt = 2 else '0';
end architecture rtl;