library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cntm13 is
  port (
    clk   : in std_ulogic;
    rst_n : in std_ulogic;
    up_i  : in std_ulogic;
    en_i  : in std_ulogic;
    cnt_o : out std_ulogic_vector(3 downto 0));
end entity;

architecture rtl of cntm13 is
begin

end architecture rtl;