library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm is
  port (
    clk   : in std_ulogic;
    rst_n : in std_ulogic;
    ctrl_i : in std_ulogic_vector(3 downto 0);
    pwm_o  : out std_ulogic);
end entity;

architecture rtl of pwm is
  signal cnt, ncnt : unsigned(3 downto 0);
begin
  cnt <= "0000" when rst_n = '0' else ncnt when rising_edge(clk);
  ncnt <= to_unsigned(0,cnt'length) when cnt = 14 else
          cnt + 1;
pwm_o <= '1' when cnt < unsigned(ctrl_i) else '0';
end architecture rtl;