library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rxautomat is
  port (
    clk          : in std_ulogic;
    rst_n        : in std_ulogic;
    rxchar       : in std_ulogic_vector(7 downto 0);
    rxchar_valid : in std_ulogic;
    led0_o       : out std_ulogic_vector(3 downto 0);
    led1_o       : out std_ulogic_vector(3 downto 0);
    led2_o       : out std_ulogic_vector(3 downto 0);
    led3_o       : out std_ulogic_vector(3 downto 0);
    send_ok_o    : out std_ulogic);
end entity;

architecture rtl of rxautomat is
begin

end architecture rtl;