library ieee;
use ieee.std_logic_1164.all;

entity top_hex is 
port ( SW   : in      std_ulogic_vector(9 downto 0);
       HEX0 : out     std_ulogic_vector(6 downto 0);
       HEX1 : out     std_ulogic_vector(6 downto 0);
       HEX2 : out     std_ulogic_vector(6 downto 0);
       LEDR : out     std_ulogic_vector(9 downto 0));
end entity;

architecture rtl of top_hex is
begin

LEDR <= SW;

bin2seg_i0: entity work.bin2seg
 port map(
    bin_i => SW(3 downto 0),
    seg_o => HEX0
);

HEX1 <= "1111111";
HEX2 <= "1111111";

end architecture rtl;