library ieee;
use ieee.std_logic_1164.all;

entity top_shift is 
port ( SW       : in  std_ulogic_vector(9 downto 0);
       KEY      : in  std_ulogic_vector(3 downto 0);
       CLOCK_50 : in  std_ulogic;
       EXP      : out std_ulogic_vector(7 downto 0);
       LEDG     : out std_ulogic_vector(3 downto 0);
       LEDR     : out std_ulogic_vector(9 downto 0));
end entity;

architecture rtl of top_shift is
  signal clk     : std_ulogic;
  signal rst_n   : std_ulogic;
  signal x       : std_ulogic;
  signal sr, srnext : std_ulogic_vector(1 downto 0);
  signal en      : std_ulogic;
begin
  -- Assign the inputs to signals with reasonable names
  clk <= CLOCK_50;
  rst_n <= KEY(0);
  x <= KEY(1);

  -------------------------
  -- The edge detector
  -------------------------
  -- Designpattern Register
  -- Create a register with two flipflops with low active
  -- asynchronous reset.
  -- D-Input is connected to srnext
  -- Q Outputs are connected to sr
  sr <= "00" when rst_n = '0' else srnext when rising_edge(clk);

  -- Implement the shift register function with next state logic
  srnext(1) <= x;
  srnext(0) <= sr(1);

  -- Compute the output function from the shift register content
  en <= sr(1) xor sr(0);

  -- Set the outputs;
  EXP <= (7 downto 4 => '0',
          3 => en,
          2 => x,
          1 => rst_n,
          0 => clk);
  LEDR <= SW;
  LEDG <= KEY;

end architecture rtl;