library ieee;
use ieee.std_logic_1164.all;

entity top_shift is 
port ( SW       : in  std_ulogic_vector(9 downto 0);
       KEY      : in  std_ulogic_vector(3 downto 0);
       CLOCK_50 : in  std_ulogic;
       EXP      : out std_ulogic_vector(7 downto 0);
       LEDG     : out std_ulogic_vector(3 downto 0);
       LEDR     : out std_ulogic_vector(9 downto 0));
end entity;

architecture rtl of top_shift is
  signal clk     : std_ulogic;
  signal rst_n   : std_ulogic;
  signal x       : std_ulogic;
  signal en      : std_ulogic;
  signal en_edge : std_ulogic;
  signal led     : std_ulogic_vector(9 downto 0);
begin
  -- Assign the inputs to signals with reasonable names
  clk <= CLOCK_50;
  rst_n <= KEY(0);
  x <= KEY(1);

  edge_inst: entity work.edge
   port map(
      clk    => clk,
      rst_n  => rst_n,
      x_i    => x,
      edge_o => en_edge);

  ringcnt_inst: entity work.ringcnt
   port map(
      clk => clk,
      rst_n => rst_n,
      en_i => en,
      y_o => led);

  en <= '1' when SW(0) = '1' else en_edge;

  -- Set the outputs;
  EXP(7 downto 4) <= led(9 downto 6);
  EXP(3 downto 0) <= (
          3 => en,
          2 => x,
          1 => rst_n,
          0 => clk);
  LEDR <= led;
  LEDG <= KEY;

end architecture rtl;