library ieee;
use ieee.std_logic_1164.all;

-- The inputs of this module are the ten switches SW
-- The outputs are connected to the red and green LEDs on the board
entity top_simple is 
port ( SW   : in      std_ulogic_vector(9 downto 0);
       LEDG : out     std_ulogic_vector(7 downto 0);
       LEDR : out     std_ulogic_vector(9 downto 0));
end entity top_simple;

architecture rtl of top_simple is
  signal d : std_ulogic_vector(3 downto 0);
  signal p, pd : std_ulogic_vector(3 downto 0);
  signal ecorr   : std_ulogic; -- Error correctable
  signal one_on  : std_ulogic;
  signal sw_corr : std_ulogic_vector(3 downto 0);
begin

LEDR(9 downto 4) <= SW(9 downto 4);
LEDR(3 downto 0) <= sw_corr;

LEDG(7) <= '0' when SW = "0000000000" else '1';
LEDG(6) <= '1' when SW(9 downto 5) = SW(4 downto 0) else '0';

d <= SW(3 downto 0);
p(0) <= d(3) xor d(1);
p(1) <= d(3) xor d(2);
p(2) <= d(2) xor d(0);
p(3) <= d(1) xor d(0);

pd <= p xor SW(7 downto 4);

with pd select
  ecorr <= '1' when "0011"|"0110"|"1001"|"1100",
           '0' when others;
with pd select
  one_on <= '1' when "0001"|"0010"|"0100"|"1000",
            '0' when others;

sw_corr(0) <= not d(0) when ecorr = '1' and pd(1 downto 0) = "00" else d(0);
sw_corr(1) <= not d(1) when ecorr = '1' and pd(1 downto 0) = "01" else d(1);
sw_corr(2) <= not d(2) when ecorr = '1' and pd(1 downto 0) = "10" else d(2);
sw_corr(3) <= not d(3) when ecorr = '1' and pd(1 downto 0) = "11" else d(3);

LEDG(5 downto 4) <= "00" when pd = "0000" else
                    "01" when ecorr = '1' else
                    "10" when one_on else
                    "11";

LEDG(3 downto 0) <= p;

end architecture rtl;