library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity txautomat is
  port (
    clk            : in std_ulogic;
    rst_n          : in std_ulogic;
    start_ok_i     : in std_ulogic
    txchar_o       : out std_ulogic_vector(7 downto 0);
    txchar_valid_o : out std_ulogic);
end entity;

architecture rtl of txautomat is
begin

end architecture rtl;