library ieee;
use ieee.std_logic_1164.all;

entity uart_rx is
  port (
    clk        : in std_ulogic;
    rst_n      : in std_ulogic;
    uart_rxd_i : in std_ulogic;
    rxd_o      : out std_ulogic_vector(7 downto 0);
    dv_o       : out std_ulogic);
end entity;

architecture rtl of uart_rx is
begin

end architecture rtl;