library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity uart_rx_baudcnt is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    sres_i  : in std_ulogic;
    en_h_o  : out std_ulogic;
    en_f_o  : out std_ulogic);
end entity;

architecture rtl of uart_rx_baudcnt is
  signal cnt, ncnt : unsigned(9 downto 0);
begin
  cnt <= "0000000000" when rst_n = '0' else ncnt when rising_edge(clk);
  ncnt <= "0000000000" when cnt = 867 or sres_i = '1' else cnt + 1;
  en_f_o <= '1' when cnt = 867 else '0';
  en_h_o <= '1' when cnt = 867/2 else '0';
end architecture rtl;