library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity uart_rx_bitcnt is
  port (
    clk        : in std_ulogic;
    rst_n      : in std_ulogic;
    edge_i     : in std_ulogic;
    en_h_i     : in std_ulogic;
    en_f_i     : in std_ulogic;
    rx_baudcnt_res_o : out std_ulogic;
    rx_shift_o : out std_ulogic;
    dv_o       : out std_ulogic);
end entity;

architecture rtl of uart_rx_bitcnt is
  signal cnt, ncnt : unsigned(3 downto 0);
begin
  cnt <= "0000" when rst_n = '0' else ncnt when rising_edge(clk);
  ncnt <= "0001" when edge_i = '1' and cnt = 0 else
    cnt + 1 when en_f_i = '1' and cnt > 0 and cnt < 10 else
    "0000" when en_h_i = '1' and cnt = 10 else cnt;

  rx_shift_o <= '1' when cnt >= 2 and cnt <= 9 and en_h_i = '1' else '0';
  dv_o <= '1' when cnt = 9 and en_f_i = '1' else '0';
  rx_baudcnt_res_o <= '1' when cnt = 0 else '0';
end architecture rtl;