library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity uart_rx_bitcnt is
  port (
    clk        : in std_ulogic;
    rst_n      : in std_ulogic;
    edge_i     : in std_ulogic;
    en_h_i     : in std_ulogic;
    en_f_i     : in std_ulogic;
    rx_baudcnt_res_o : out std_ulogic;
    rx_shift_o : out std_ulogic;
    dv_o       : out std_ulogic);
end entity;

architecture rtl of uart_rx_bitcnt is
begin
end architecture rtl;