library ieee;
use ieee.std_logic_1164.all;

entity uart_rx_edge is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    rxd_i   : in std_ulogic;
    rxd_o   : out std_ulogic;
    edge_o  : out std_ulogic);
end entity;

architecture rtl of uart_rx_edge is
  signal sr, nsr : std_ulogic_vector(1 downto 0);
begin
  sr <= "00" when rst_n = '0' else nsr when rising_edge(clk);
  nsr <= rxd_i & sr(1);
  rxd_o <= sr(0);
  edge_o <= '1' when sr = "01" else '0';
end architecture rtl;