library ieee;
use ieee.std_logic_1164.all;

entity uart_rx_shift is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    shift_i : in std_ulogic;
    ser_i   : in std_ulogic;
    d_o     : out std_ulogic_vector(7 downto 0));
end entity;

architecture rtl of uart_rx_shift is
begin
end architecture rtl;