library ieee;
use ieee.std_logic_1164.all;

entity uart_tx_shift is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    start_i : in std_ulogic;
    en_i    : in std_ulogic;
    d_i     : in std_ulogic_vector(7 downto 0);
    tx_o    : out std_ulogic);
end entity;

architecture rtl of uart_tx_shift is
begin

end architecture rtl;