library ieee;
use ieee.std_logic_1164.all;

entity uart_tx_shift is
  port (
    clk     : in std_ulogic;
    rst_n   : in std_ulogic;
    start_i : in std_ulogic;
    en_i    : in std_ulogic;
    d_i     : in std_ulogic_vector(7 downto 0);
    tx_o    : out std_ulogic);
end entity;

architecture rtl of uart_tx_shift is
  signal sr, srn : std_ulogic_vector(8 downto 0);
begin
  sr <= (others => '1') when rst_n = '0' else srn when rising_edge(clk);
  srn <= d_i & '0' when start_i = '1' else
         '1' & sr(8 downto 1) when en_i = '1' else sr;
  tx_o <= sr(0);
end architecture rtl;