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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cntm13 is
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
up_i : in std_ulogic;
en_i : in std_ulogic;
cnt_o : out std_ulogic_vector(3 downto 0));
end entity;
architecture rtl of cntm13 is
signal cnt, ncnt : unsigned(3 downto 0);
begin
cnt <= to_unsigned(0,cnt'length) when rst_n = '0' else ncnt when en_i = '1' and rising_edge(clk);
ncnt <= to_unsigned(0,cnt'length) when up_i = '1' and cnt = 12 else
to_unsigned(12,cnt'length) when up_i = '0' and cnt = 0 else
cnt + 1 when up_i = '1' else
cnt - 1;
cnt_o <= std_ulogic_vector(cnt);
end architecture rtl;
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