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library ieee;
use ieee.std_logic_1164.all;
entity ringcnt is
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
en_i : in std_ulogic;
y_o : out std_ulogic_vector(9 downto 0));
end entity;
architecture rtl of ringcnt is
signal rc, rcn : std_ulogic_vector(9 downto 0);
begin
rc <= "1000000000" when rst_n = '0' else rcn when rising_edge(clk);
rcn <= rc when en_i = '0' else rc(0) & rc(9 downto 1);
y_o <= rc;
end architecture rtl;
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