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library ieee;
use ieee.std_logic_1164.all;
entity top_count is
port ( SW : in std_ulogic_vector(9 downto 0);
KEY : in std_ulogic_vector(3 downto 0);
CLOCK_50 : in std_ulogic;
HEX0 : out std_ulogic_vector(6 downto 0);
EXP : out std_ulogic_vector(7 downto 0);
LEDG : out std_ulogic_vector(3 downto 0);
LEDR : out std_ulogic_vector(9 downto 0));
end entity;
architecture rtl of top_count is
signal clk : std_ulogic;
signal rst_n : std_ulogic;
signal x : std_ulogic;
signal en : std_ulogic;
signal pwm : std_ulogic;
signal cnt : std_ulogic_vector(3 downto 0);
begin
-- Assign the inputs to signals with reasonable names
clk <= CLOCK_50;
rst_n <= KEY(0);
x <= KEY(1);
cnt1sec_inst: entity work.cnt1sec
port map(
clk => clk,
rst_n => rst_n,
en_o => en
);
ringcnt_inst: entity work.ringcnt
port map(
clk => clk,
rst_n => rst_n,
en_i => en,
y_o => LEDR
);
cntm13_inst: entity work.cntm13
port map(
clk => clk,
rst_n => rst_n,
up_i => x,
en_i => en,
cnt_o => cnt
);
pwm_inst: entity work.pwm
port map(
clk => clk,
rst_n => rst_n,
ctrl_i => SW(3 downto 0),
pwm_o => pwm
);
bin2seg_inst: entity work.bin2seg
port map(
bin_i => cnt,
seg_o => HEX0
);
-- Set the outputs;
EXP(7 downto 4) <= cnt;
EXP(3 downto 0) <= (3 => en,
2 => pwm,
1 => rst_n,
0 => clk);
LEDG(3) <= pwm;
LEDG(2 downto 0) <= KEY(2 downto 0);
end architecture rtl;
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