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library ieee;
use ieee.std_logic_1164.all;
entity top_uart is
port ( SW : in std_ulogic_vector(9 downto 0);
KEY : in std_ulogic_vector(3 downto 0);
CLOCK_50 : in std_ulogic;
UART_RXD : in std_ulogic;
UART_TXD : out std_ulogic;
EXP : out std_ulogic_vector(7 downto 0);
LEDG : out std_ulogic_vector(3 downto 0);
LEDR : out std_ulogic_vector(9 downto 0));
end entity;
architecture rtl of top_uart is
signal clk : std_ulogic;
signal rst_n : std_ulogic;
signal en, txd : std_ulogic;
signal start : std_ulogic;
begin
-- Assign the inputs to signals with reasonable names
clk <= CLOCK_50;
rst_n <= KEY(0);
edge_inst: entity work.edge
port map(
clk => clk,
rst_n => rst_n,
x_i => KEY(1),
edge_o => start
);
baudcnt_inst: entity work.baudcnt
port map(
clk => clk,
rst_n => rst_n,
start_i => start,
en_o => en
);
uart_tx_shift_inst: entity work.uart_tx_shift
port map(
clk => clk,
rst_n => rst_n,
start_i => start,
en_i => en,
d_i => SW(7 downto 0),
tx_o => txd
);
-- Set the outputs;
EXP(7 downto 4) <= "0000";
EXP(3 downto 0) <= (3 => txd,
2 => en,
1 => rst_n,
0 => clk);
UART_TXD <= txd;
LEDR <= SW;
LEDG <= KEY;
end architecture rtl;
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