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library ieee;
use ieee.std_logic_1164.all;
entity uart_rx is
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
uart_rxd_i : in std_ulogic;
rxd_o : out std_ulogic_vector(7 downto 0);
dv_o : out std_ulogic);
end entity;
architecture rtl of uart_rx is
signal edge, shift, baud_en_f, baud_en_h, baud_res : std_ulogic;
signal uart_rxd_sync : std_ulogic;
begin
uart_rx_edge_inst: entity work.uart_rx_edge
port map(
clk => clk,
rst_n => rst_n,
rxd_i => uart_rxd_i,
rxd_o => uart_rxd_sync,
edge_o => edge
);
uart_rx_shift_inst: entity work.uart_rx_shift
port map(
clk => clk,
rst_n => rst_n,
shift_i => shift,
ser_i => uart_rxd_sync,
d_o => rxd_o
);
uart_rx_baudcnt_inst: entity work.uart_rx_baudcnt
port map(
clk => clk,
rst_n => rst_n,
sres_i => baud_res,
en_h_o => baud_en_h,
en_f_o => baud_en_f
);
uart_rx_bitcnt_inst: entity work.uart_rx_bitcnt
port map(
clk => clk,
rst_n => rst_n,
edge_i => edge,
en_h_i => baud_en_h,
en_f_i => baud_en_f,
rx_baudcnt_res_o => baud_res,
rx_shift_o => shift,
dv_o => dv_o
);
end architecture rtl;
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