% !TEX root = dt-slides-dt.tex


\section{Zähler}

\begin{frame}
\frametitle{Zähler}
\center
\Huge Zähler
\end{frame}


\begin{frame}
\frametitle{Addierer}
\begin{block}{Arraydarstellung}
In Schaltplänen zeichne ich Addierer mit Eingängen a und b und dem Ausgang y. Diese Ein- und Ausgänge repräsentieren jeweils ein Array von einzelnen digitalen Signalen. Die Anzahl der Bit muss explizit angegeben werden oder ist aus dem Kontext zu entnehmen. Als Implementierung kann die Carry-Ripple-Adder Architektur angenommen werden.
\end{block}
\vspace{1cm}
\center
\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]	
\draw (0,0) rectangle (1.2,2.5);
\draw (0,0.5) node [anchor=west] {b};
\draw (0,2) node [anchor=west] {a};
\draw (1.2,1.25) node [anchor=east] {y};
\draw (0.6,1.25) node {+};
\end{tikzpicture}
\hspace{3cm}
\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]

	\draw (0,0) rectangle (1.2,2.5) ;
	% The left inputs
	\draw (0,2.5) 
	\foreach \name in {$a_3$, $a_2$, $a_1$, $a_0$}
	{
	   ++(0,-0.22) node [anchor=west] {\name}
	}
	;
	\draw (0,0) 
	\foreach \name in {$b_0$, $b_1$, $b_2$, $b_3$}
	{
	   ++(0,0.22) node [anchor=west] {\name}
	}
	;
	% The y output
	\draw (1.2,0.7)
	\foreach \name in {$y_0$, $y_1$, $y_2$, $y_3$}
	{
	   ++(0,0.22) node [anchor=east] {\name}
	}
	;
	\draw(0.5,1.25) node {+};
\end{tikzpicture} 
\end{frame}

\begin{frame}
\frametitle{Zähler}
\center
\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]

\draw (0,0) rectangle (1.2,2.5);
\draw (0,0.5) node [anchor=west] (b) {b};
\draw (0,2) node [anchor=west] (a) {a};
\draw (1.2,1.25) node [anchor=east] (y) {y};
\draw (0.6,1.25) node {+};
\draw (y.east) -- node[above] {d[3..0]} ++(right:1) node[shape=ff, anchor=D] (r0) {};
\draw (r0.Q) -- node[above] {q[3..0]} ++(right:1)  node[contact] (c0) {};
\draw (a.west) -- ++(left:1) -- ++(up:1) -| (c0);
\draw (c0) -- ++(right:1) node[anchor=west] {y[3..0]};
\draw (b.west) -- ++(left:1) node [anchor=east] {$1_D$};
\draw (r0.R) -- ++(down:1) node[anchor=north] {rst\_n};
\draw (r0.CLK) -- ++(left:0.25) -- ++(down:1) node[anchor=north] {clk};

\end{tikzpicture} 

\begin{exampleblock}{Modulo 16 Zähler}
Bei der Schaltung wird ein 4-Bit Addierer und ein 4-Bit Register verwendet. Durch die Modulo 16 Addition wird dies ein Modulo 16 Zähler, der von 0 bis 15 zählt und dann wieder bei 0 anfängt. Im Timingdiagramm sind die 4-Bit Arraysignale d und q als vorzeichenlose Dezimalzahl dargestellt.
\end{exampleblock}

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
q[3..0] & 8D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}2D{11}2D{12}2D{13}2D{14}2D{15}2D{0}2D{1}2D{2}2D{3}2D{4} \\
d[3..0] & 8D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}2D{11}2D{12}2D{13}2D{14}2D{15}2D{0}2D{1}2D{2}2D{3}2D{4}2D{5} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}


\end{frame}

\begin{frame}
\frametitle{Synchrones Laden/synchroner Reset am Beispiel Zähler}
\center
\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]

\draw (0,0) rectangle (1.2,2.5);
\draw (0,0.5) node [anchor=west] (b) {b};
\draw (0,2) node [anchor=west] (a) {a};
\draw (1.2,1.25) node [anchor=east] (y) {y};
\draw (0.6,1.25) node {+};
\draw (y.east) --  ++(right:1) node[shape=mux,anchor=izero] (m0) {};
\draw (m0.output) -- node[above] {d} ++(right:1) node[shape=ff, anchor=D] (r0) {};
\draw (r0.Q) -- node[above] {q} ++(right:1)  node[contact] (c0) {};
\draw (a.west) -- ++(left:1) -- ++(up:1) -| (c0);
\draw (c0) -- ++(right:1) node[anchor=west] {y};
\draw (b.west) -- ++(left:1) node [anchor=east] {$1_D$};
\draw (r0.R) -- ++(down:1) node[anchor=north] {rst\_n};
\draw (r0.CLK) -- ++(left:0.25) -- ++(down:1) node[anchor=north] {clk};

\draw (m0.ione) -- ++(left:0.25) node[anchor=east] {$5_D$};
\draw (m0.sel) -- ++(down:1) node[anchor=north] {ld\_i};

\end{tikzpicture} 
\vspace{1cm};

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
ld\_i & 27L6H10L \\
q & 8D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}6D{5}2D{6}2D{7}2D{8}2D{9}2D{10}2D{11} \\
d & 8D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}D{11}6D{5}D{6}2D{7}2D{8}2D{9}2D{10}2D{11} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}
\end{frame}

\begin{frame}
\frametitle{Synchrones Enable am Beispiel Zähler}
\center
\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]

\draw (0,0) rectangle (1.2,2.5);
\draw (0,0.5) node [anchor=west] (b) {b};
\draw (0,2) node [anchor=west] (a) {a};
\draw (1.2,1.25) node [anchor=east] (y) {y};
\draw (0.6,1.25) node {+};
\draw (y.east) --  ++(right:1) node[shape=mux,anchor=ione] (m0) {};
\draw (m0.output) -- node[above] {d} ++(right:1) node[shape=ff, anchor=D] (r0) {};
\draw (r0.Q) -- node[above] {q} ++(right:1)  node[contact] (c0) {};
\draw (m0.izero) -- ++(left:0.25) -- ++(up:1.25) node[contact] (c1) {};
\draw (a.west) -- ++(left:1) |- (c1) -| (c0);
\draw (c0) -- ++(right:1) node[anchor=west] {y};
\draw (b.west) -- ++(left:1) node [anchor=east] {$1_D$};
\draw (r0.R) -- ++(down:1) node[anchor=north] {rst\_n};
\draw (r0.CLK) -- ++(left:0.25) -- ++(down:1) node[anchor=north] {clk};

\draw (m0.sel) -- ++(down:1) node[anchor=north] {en\_i};

\end{tikzpicture} 
\vspace{1cm};

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
en\_i & 27H6L15H \\
q & 8D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}8D{10}2D{11}2D{12}2D{13}2D{14}2D{15}2D{0}2D{1}\\
d & 8D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}D{11}6D{10}D{11}2D{12}2D{13}2D{14}2D{15}2D{0}2D{1}2D{2} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}
\end{frame}

\begin{frame}
\frametitle{Zähler, der bei 9 stehenbleibt}

\begin{block}{Kombination aus synchronem Laden mit Vergleicher und Zähler}
In dieser Schaltung wird das Konzept des synchronen Ladens mit einem Vergleicher bei einem Zähler kombiniert.
\end{block}
\vspace{3mm};
\begin{circuitikz}
%\ctikzset{tripoles/european not symbol=ieee circle}
\ctikzset{flipflops/scale=0.5}
\draw(0,0) node[muxdemux,
muxdemux def={Rh=1, Lh=2, NL=2, NB=1,w=1},
muxdemux label = {L1=0, L2=1}] (mux) {};
\draw (mux.rpin 1) -- node[above] {d} ++(right:1) node[flipflop D,
flipflop def={td=R, nd=1}, anchor = pin 1] (ff) {};

\draw (mux.lpin 1) -- ++(left:1) node[muxdemux,
muxdemux def={Lh=3,Rh=3,NL=2,NB=0,w=2},
muxdemux label = {L1=a,L2=b,R1=y},
anchor=rpin 1] (add) {+};
\draw (add.lpin 2) node [anchor=east] {$1_D$};
\draw (ff.pin 6) -- node[above] {q} ++(right:1) node[circ] (c0) {};
\draw (add.lpin 1) -- ++(up:0.8) -| (c0);
\draw (mux.bpin 1) -- node[right] {sel} ++(down:0.5) node[muxdemux,
muxdemux def={Lh=2,Rh=2,NL=0,NB=1,NT=1,NR=0,w=2},
muxdemux label = {T1=y,B1=x},
anchor=tpin 1] (vgl) {= $9_D$};
\draw (c0) |- (vgl.bpin 1);
\draw (c0) -- ++(right:1) node[anchor=west] {y};
\draw (mux.lpin 2) node[anchor=east] {$9_D$};
\draw (ff.down) -- ++(down:0.5) node[anchor=north] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
\end{circuitikz}
\vspace{3mm};
\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
sel & 24L26H \\
q & 8D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}26D{9}\\
d & 8D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}28D{9} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\end{frame}

\begin{frame}
\frametitle{Rückwärtszähler}
\begin{block}{Rückwärtszähler}
Durch die Addition von -1D = 1111B wird der 4-Bit Modulo 16 Zähler zu einem Modulo 16 Rückwärtszähler. Die Interpretation im Timingdiagramm ist immer noch eine vorzeichenlose Dezimalzahl. Bei einer Interpretation als Zweierkomplement wäre es immer noch ein Rückwärtszähler, allerdings wäre die +15D dann die -1D u.s.w.
\end{block}

\hspace{2cm}
\begin{circuitikz}
%\ctikzset{tripoles/european not symbol=ieee circle}
\ctikzset{flipflops/scale=0.5}
\draw (0,0) node[flipflop D,
flipflop def={td=R, nd=1}] (ff) {};
\draw (ff.pin 1) -- node[above] {d} ++(left:1) node[muxdemux,
muxdemux def={Lh=3,Rh=3,NL=2,NB=0,w=2},
muxdemux label = {L1=a,L2=b,R1=y},
anchor=rpin 1] (add) {+};
\draw (add.lpin 2) node [anchor=east] {$-1_D$};
\draw (ff.pin 6) -- node[above] {q} ++(right:1) node[circ] (c0) {};
\draw (add.lpin 1) -- ++(up:0.8) -| (c0);
\draw (c0) -- ++(right:1) node[anchor=west] {y};
\draw (ff.down) -- ++(down:0.5) node[anchor=north] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
\end{circuitikz}

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
q[3..0] & 8D{0}2D{15}2D{14}2D{13}2D{12}2D{11}2D{10}2D{9}2D{8}2D{7}2D{6}2D{5}2D{4}2D{3}2D{2}2D{1}2D{0}2D{15}2D{14}2D{13}2D{12}2D{11} \\
d[3..0] & 8D{15}2D{14}2D{13}2D{12}2D{11}2D{10}2D{9}2D{8}2D{7}2D{6}2D{5}2D{4}2D{3}2D{2}2D{1}2D{0}2D{15}2D{14}2D{13}2D{12}2D{11} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\end{frame}

\begin{frame}
\frametitle{Modulo 13 Zähler}

\begin{block}{Modulo 13 Zähler}
Der Modulo 13 Zähler zählt von 0 bis 12 und fängt dann wieder bei 0 an.
\end{block}
\vspace{3mm};
\begin{circuitikz}
%\ctikzset{tripoles/european not symbol=ieee circle}
\ctikzset{flipflops/scale=0.5}
\draw(0,0) node[muxdemux,
muxdemux def={Rh=1, Lh=2, NL=2, NB=1,w=1},
muxdemux label = {L1=0, L2=1}] (mux) {};
\draw (mux.rpin 1) -- node[above] {d} ++(right:1) node[flipflop D,
flipflop def={td=R, nd=1}, anchor = pin 1] (ff) {};

\draw (mux.lpin 1) -- ++(left:1) node[muxdemux,
muxdemux def={Lh=3,Rh=3,NL=2,NB=0,w=2},
muxdemux label = {L1=a,L2=b,R1=y},
anchor=rpin 1] (add) {+};
\draw (add.lpin 2) node [anchor=east] {$1_D$};
\draw (ff.pin 6) -- node[above] {q} ++(right:1) node[circ] (c0) {};
\draw (add.lpin 1) -- ++(up:0.8) -| (c0);
\draw (mux.bpin 1) -- node[right] {sel} ++(down:0.5) node[muxdemux,
muxdemux def={Lh=2,Rh=2,NL=0,NB=1,NT=1,NR=0,w=2},
muxdemux label = {T1=y,B1=x},
anchor=tpin 1] (vgl) {= $12_D$};
\draw (c0) |- (vgl.bpin 1);
\draw (c0) -- ++(right:1) node[anchor=west] {y};
\draw (mux.lpin 2) node[anchor=east] {$0_D$};
\draw (ff.down) -- ++(down:0.5) node[anchor=north] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
\end{circuitikz}
\vspace{3mm};
\begin{tikztimingtable}
clk & 2L22{CC}\\
rst\_n & 7L39H \\
sel & 30L2H14L \\
q & 8D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}2D{11}2D{12}2D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}\\
d & 8D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{7}2D{8}2D{9}2D{10}2D{11}2D{12}2D{0}2D{1}2D{2}2D{3}2D{4}2D{5}2D{6}2D{8}\\\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\end{frame}




\begin{frame}
\frametitle{Ladbares Schieberegister}

\begin{block}{Arraydarstellung}
Hier ein Ladbares Schieberegister in einer Arraydarstellung. Die \glqq shr\grqq\, Funktion stellt das Schieben nach Rechts dar. Links wird dabei eine 0 ergänzt.
\end{block}

\begin{circuitikz}
%\ctikzset{tripoles/european not symbol=ieee circle}
\ctikzset{flipflops/scale=0.5}
\draw(0,0) node[muxdemux,
muxdemux def={Rh=1, Lh=2, NL=2, NB=1,w=1},
muxdemux label = {L1=0, L2=1}] (mux) {};
\draw (mux.rpin 1) -- node[above] {d[2..0]} ++(right:1) node[flipflop D,
flipflop def={td=R, nd=1}, anchor = pin 1] (ff) {};

\draw (mux.lpin 1) -- ++(left:1) node[muxdemux,
muxdemux def={Lh=3,Rh=3,NL=1,NR=1,NB=0,w=2},
muxdemux label = {L1=x, R1=y},
anchor=rpin 1] (shr) {shr};

\draw (ff.pin 6) -- node[above] {q[2..0]} ++(right:1) node[circ] (c0) {};

\draw (mux.bpin 1) -- ++(down:0.5) node[anchor=north] {ld\_i};
\draw (c0) -- ++(right:1) coordinate (cbs) -- ++(down:0.9);

\draw[thin] (cbs) ++(down:0.1) -- ++(0.25,-0.25) -- node[above] {$q_2$} ++(right:1);
\draw (cbs) ++(down:0.5) -- ++(0.25,-0.25) -- node[above] {$q_1$} ++(right:1);
\draw (cbs) ++(down:0.9) -- ++(0.25,-0.25) -- node[above] {$q_0$} ++(right:1) node[anchor=west] {ser\_o};
\draw (shr.lpin 1) -- ++(up:1.2) -| (c0);
\draw (mux.lpin 2) node[anchor=east] {d\_i[2..0]};
\draw (ff.down) -- ++(down:0.5) node[anchor=north] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
\end{circuitikz}
\vspace{5mm}
\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
ld\_i & 17L2H12L2H10L2H3L \\
d\_i[2..0] & 13D{000}8D{111}14D{101}13D{000} \\
q[2..0] & 18D{000}2D{111}2D{011}2D{001}8D{000}2D{101}2D{010}2D{001}10D{000} \\
ser\_o & 18L6H8L2H2L2H10L \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}
\end{frame}


\begin{frame}
\frametitle{Akkumulator}
\begin{itemize}
\item Am Dateneingang $d_i$ kommen in jedem Takt neue Daten an
\item Die Werte $d_i$ am Dateneingang werden aufaddiert $y_{n+1} = y_n + d_i$
\item Die Summe $y$ ist am aus $y_o$ sichtbar
\item Wenn das Signal sres\_i auf '1' gesetzt wird, dann soll die Summe auf 0 zurückgesetzt werden
\end{itemize}

\begin{circuitikz}
%\ctikzset{tripoles/european not symbol=ieee circle}
\ctikzset{flipflops/scale=0.5}
\draw(0,0) node[muxdemux,
muxdemux def={Rh=1, Lh=2, NL=2, NB=1,w=1},
muxdemux label = {L1=0, L2=1}] (mux) {};
\draw (mux.rpin 1) -- node[above] {d} ++(right:1) node[flipflop D,
flipflop def={td=R, nd=1}, anchor = pin 1] (ff) {};

\draw (mux.lpin 1) -- ++(left:1) node[muxdemux,
muxdemux def={Lh=3,Rh=3,NL=2,NB=0,w=2},
muxdemux label = {L1=a,L2=b,R1=y},
anchor=rpin 1] (add) {+};
\draw (ff.pin 6) -- node[above] {q} ++(right:1) node[circ] (c0) {};
\draw (add.lpin 1) -- ++(up:0.8) -| (c0);
\draw (mux.bpin 1) -- ++(down:0.1) node[anchor=north] {sres\_i};

\draw (add.lpin 2) -- ++(left:0.1) node[muxdemux,
muxdemux def={Lh=1,Rh=1,NL=1,NR=1,NB=0,w=4},
muxdemux label = {L1=x[7..0],R1=y[19..0]},
anchor=rpin 1] (sext) {sext};
\draw (sext.lpin 1) node[anchor=east] {d\_i};

\draw (c0) -- ++(right:1) node[anchor=west] {y};
\draw (mux.lpin 2) node[anchor=east] {$0_D$};
\draw (ff.down) -- ++(down:0.5) node[anchor=north] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
\end{circuitikz}

\vspace{3mm}

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
sres\_i & 17L2H14L2H10L2H3L \\
$d_i$[7..0] & 13D{2}2D{10}2D{3}2D{7}8D{5}14D{100}9D{1} \\
$y_o$[19..0] & 8D{0}2D{2}2D{4}2D{6}2D{16}2D{19}2D{0}2D{5}2D{10}2D{15}2D{20}2D{120}2D{220}2D{320}2D{0}2D{100}2D{200}2D{300}2D{301}2D{302}2D{0}2D{1} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\begin{block}{Bitbreite}
Der Block \glqq sext\grqq\, macht eine Stellenerweiterung von 8 auf 20 Bit. Mit 20 Bit Bitbreite können mindestens 4096 Datenwerte akkumuliert werden, wenn d\_i vorzeichenlos ist.
\end{block}

\end{frame}




\begin{frame}
\frametitle{Beispiel: Maximalwert}
\begin{itemize}
\item Am Dateneingang $d_i$ kommen in jedem Takt neue Daten an
\item Die Schaltung merkt sich den maximal auftretenden Wert $d_i$
\item Der Maximalwert ist am Ausgang $y_o$ sichtbar
\item Wenn das Signal sres\_i auf '1' gesetzt wird, dann wird der gespeicherte Maximalwert auf 0 zurückgesetzt
\end{itemize}

\vspace{5cm}

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
sres\_i & 17L2H14L2H10L2H3L \\
$d_i$[7..0] & 2D{88}2D{19}2D{7}2D{4}2D{21}2D{45}2D{19}2D{3}2D{48}2D{3}2D{129}2D{91}2D{67}2D{188}2D{13}2D{4}2D{99}2D{103}8D{9}4D{177}2D{219}2D{220}2D{221} \\
$y_o$[7..0] & 8D{0}2D{4}2D{21}6D{45}2D{0}2D{3}6D{129}6D{188}2D{0}10D{103}2D{0}2D{177}2D{219}2D{220}2D{221}  \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,4}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}
\end{frame}


\begin{frame}
\frametitle{Beispiel: Enablegenerator}
\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
y &  12L2H6L2H6L2H6L2H6L2H2L \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,3}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\vspace{6cm}

\end{frame}


\begin{frame}
\frametitle{Beispiel: Enablegenerator - Basis Ringzähler}
\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
y &  12L2H6L2H6L2H6L2H6L2H2L \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,3}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\vspace{6cm}

\end{frame}

\begin{frame}
\frametitle{Beispiel: Enablegenerator - Basis Modulo 4 Zähler}
\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
y &  12L2H6L2H6L2H6L2H6L2H2L \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,3}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}

\vspace{6cm}

\end{frame}

\begin{frame}
\frametitle{Synchrones Schaltungsdesign}

\begin{columns}
\begin{column}{0.5\textwidth}
\begin{circuitikz}
%\ctikzset{tripoles/european not symbol=ieee circle}
\ctikzset{flipflops/scale=0.5}
\foreach \p in {(0,0), (2,3.9), (3.9,4)}
{
\draw \p node[flipflop D,
flipflop def={td=R, nd=1}] (ff) {};
\draw (ff.down) -- ++(down:0.5) node[anchor=north] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
}
\foreach \p in {(0,3), (2,0.5), (4,0)}
{
\draw \p node[flipflop D,
flipflop def={tu=S, nu=1}] (ff) {};
\draw (ff.up) -- ++(up:0.5) node[anchor=south] {rst\_n};
\draw (ff.pin 3) node[anchor=east] {clk};
}
\end{circuitikz}
\end{column}
\begin{column}{0.5\textwidth}
\begin{itemize}
\item Alle Flipflops an der gleichen Taktleitung
\item Alle Flipflops an der gleichen Resetleitung
\item Keine Logik in der Reset- oder Taktleitung
\end{itemize}
\end{column}
\end{columns}
 
\end{frame}



\begin{frame}
\frametitle{Synchrones Enable}
\hspace{2cm}
\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]
\draw (0,0) node[shape=ff, anchor=D] (r0) {};
\draw (0,2) node[shape=ff, anchor=D] (r1) {};
\draw (r0.Q) -- node[above] {q0} ++(right:1) node[and gate,anchor = input 2] (and) {};
\draw (r1.Q) -- node[above] {q1} ++(right:0.5) |- (and.input 1);
\draw (r1.D) -- ++(left:0.5) node[xor gate, anchor = output] (xor) {};
\draw (r0.D) -- ++(left:0.5) node[not gate, anchor = output] (inv1) {};
\draw (xor.input 1) --  ++(left:0.25) node[anchor=east] {q1};
\draw (xor.input 2) --  ++(left:0.25) node[anchor=east] {q0};
\draw (inv1.input) -- ++(left:0.25) node[anchor=east] {q0};
\draw (and.output) -- node[above] {en} ++(right:0.5);

\draw (7,2) node[shape=ff, anchor=D] (r2) {};
\draw (r2.D)  ++(left:2) node[not gate, anchor = output] {};
\draw (r2.Q) -- ++(right:0.5) node[anchor=west] {y};

\end{tikzpicture} 

\vspace{2cm}

\begin{tikztimingtable}
clk & 2L25{CC}\\
rst\_n & 7L42H \\
en &  12L2H6L2H6L2H6L2H6L2H2L \\
y &   14L8H8L8H8L4H \\
cnt = q1q0 &  8D{00}2D{01}2D{10}2D{11}2D{00}2D{01}2D{10}2D{11}2D{00}2D{01}2D{10}2D{11}2D{00}2D{01}2D{...} \\
\extracode
\begin{pgfonlayer}{background}
\begin{scope}[semitransparent ,semithick]
\vertlines[black]{2,4,...,48}
\horlines{2,3,...,3}
\end{scope}
\end{pgfonlayer}
\end{tikztimingtable}


\end{frame}