% !TEX root = dt-slides-dt.tex
\section{Reale Gatter}

\begin{frame}
\frametitle{Reale Gatter}
\begin{center}
\LARGE Reale Gatter
\end{center}
\end{frame}

\begin{frame}
\frametitle{MOS Transistoren NMOS / PMOS / CMOS / Beispiel Inverter}
\centering
\begin{tabular}{ccc}
\begin{circuitikz}
\draw (0,4) node[pigfete] (pmos) {PMOS};
\draw (0,0) node[nigfete] (nmos) {NMOS};
\draw (nmos.G) node[anchor=east] {Gate};
\draw (nmos.S) node[anchor=south west] {Source};
\draw (nmos.D) node[anchor=north west] {Drain};
\draw (pmos.G) node[anchor=east] {Gate};
\draw (pmos.S) node[anchor=north west] {Source};
\draw (pmos.D) node[anchor=south west] {Drain};
\draw (nmos.G) -- (pmos.G) node[circ, midway] (c0) {};
\draw (c0) -- ++(left:2) node[anchor=east] {Ui};
\draw (nmos.D) -- (pmos.D) node[circ,midway] (c1) {};
\draw (c1) -- ++(right:2) node[anchor=west] {Uo};
\draw (nmos.S) node[circ] {} -- +(right:2) -- +(left:2) node[anchor=north] {Gnd};
\draw (pmos.S) node[circ] {} -- +(right:2) -- +(left:2) node[anchor=south] {Vdd};
\end{circuitikz}
&
\begin{circuitikz}
\draw (0,0) to[ccsw] (0,3) to[cosw] (0,6);
\draw (0,3) node[anchor=east] {Ui = Vdd};
\draw (0,3) node[anchor=west] {Uo = Gnd};
\end{circuitikz}
&
\begin{circuitikz}
\draw (0,0) to[cosw] (0,3) to[ccsw] (0,6);
\draw (0,3) node[anchor=east] {Ui = Gnd};
\draw (0,3) node[anchor=west] {Uo = Vdd};
\end{circuitikz}\\
\end{tabular}

\end{frame}


\begin{frame}
\frametitle{MOS Transistoren}
\includegraphics[width=\textwidth]{realegatter/rg-mos}
\end{frame}

\begin{frame}
\frametitle{Periodensystem}
\includegraphics[width=\textwidth]{realegatter/rg-periodensystem}
\end{frame}

\begin{frame}
\frametitle{Xilinx Virtex 5 FPGA}
\includegraphics[width=\textwidth]{realegatter/rg-virtex5-metalstack}
\end{frame}

\begin{frame}
\frametitle{Xilinx Virtex 5 FPGA}
\includegraphics[width=\textwidth]{realegatter/rg-virtex5-twotrans}
\end{frame}

\begin{frame}
\frametitle{Xilinx Virtex 5 FPGA}
\includegraphics[width=0.7\textwidth]{realegatter/rg-virtex5-trans}
\end{frame}

\begin{frame}
\frametitle{Technology Scaling - Bernard Meyerson (IBM) }
\includegraphics[width=0.9\textwidth]{realegatter/rg-meyerson}
\end{frame}


\begin{frame}
\frametitle{NMOS Transistor Kennlinie}
\includegraphics[width=0.7\textwidth]{realegatter/rg-kennnmos}
\vspace{0.5cm}

\hspace{1cm}\includegraphics[width=0.1\textwidth]{realegatter/rg-nmos}
\vspace{4cm}
\end{frame}

\begin{frame}
\frametitle{Inverter aus MOS Transistoren}
\includegraphics[width=\textwidth]{realegatter/rg-inverter}
\end{frame}

\begin{frame}
\frametitle{CMOS Inverter - statische Kennlinie}
\includegraphics[width=\textwidth]{realegatter/rg-kennstat}
\end{frame}

\begin{frame}
\frametitle{CMOS Inverter - Verzögerungszeit (dynamisch)}
\includegraphics[width=\textwidth]{realegatter/rg-kenndyn}
\end{frame}

\begin{frame}
\frametitle{CMOS - Ausgänge zusammenschalten}
\includegraphics[height=0.7\textheight]{realegatter/rg-kurzschluss}
\end{frame}

\begin{frame}
\frametitle{74HC00 - 4 fach NAND Gatter}
\includegraphics[width=0.7\textwidth]{realegatter/74hc00}

\tiny{source: © Raimond Spekking / CC BY-SA 4.0 (via Wikimedia Commons) \url{https://commons.wikimedia.org/wiki/File:Seagate_ST351A-X_-_controller_-_STMicroelectronics_74HC00-1963.jpg}}

Labor: \url{https://www.hs-augsburg.de/homes/beckmanf/dokuwiki/doku.php?id=dtlab_t1}


\end{frame}

\begin{frame}
\frametitle{Verzögerung A}

\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]
\draw (0,0) node[or gate] (or) {};
\draw (or.input 1) -- ++(left:1cm) node[anchor=east] {a};
\draw (or.input 2) -- ++(left:1cm) node[anchor=east] {b};
\draw (or.output) -- ++(right:3mm) node[anchor=west] {y};
\end{tikzpicture} 
\hspace{1cm}
$t_p = 1 ns$
\vspace{2cm}


\scalebox{2.5}{
\begin{tikztimingtable}
a & 4{L}15H\\
b & 10L2H10L \\
y & 6L14H\\
\extracode
\begin{pgfonlayer}{background} 
\begin{scope}[semitransparent ,semithick]
%\vertlines[red]{2.1,4.1,...,10.1}
\vertlines[blue]{2,4,...,20} 
\end{scope}
% Draw the ruler 
\draw[->] (all rows.south west) ++(down:0.7) node (rulerbegin) {} -- (all rows.south east |- rulerbegin)  -- ++(7mm,0) node[anchor=north] {\small t/ns};
\draw
(rulerbegin)
\foreach \xtext in {1,2,...,9}{
++(2,0) node[anchor=north] {\small \xtext}};
\end{pgfonlayer}
\end{tikztimingtable}
}%scalebox

\end{frame}

\begin{frame}
\frametitle{Verzögerung B}

\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]
\draw (0,0) node[and gate] (g0) {};
\draw (2,0) node[and gate] (g1) {};
\draw (4,0) node[and gate] (g2) {};
\draw (g0.input 2) -- ++(left:5mm) node[contact] (c) {} -- ++(left:5mm) node[anchor=east] {a};
\draw (g0.input 1) -- ++(left:1cm) node[anchor=east] {b};
\draw (g0.output) -- ++(right:3mm) |- node[anchor=south] {x} (g1.input 1);
\draw (g1.output) -- ++(right:3mm) |- node[anchor=south] {y} (g2.input 1);
\draw (g2.output) -- ++(right:3mm) node[anchor=west] {z};
\draw (g2.input 2) -- ++(left:3mm) -- ++(down:1) -| (c);
\draw (g1.input 2) -- ++(left:3mm) -- ++(down:1) node[contact]{};
\end{tikzpicture}
\hspace{1cm}
$t_{pLH} = 1ns,  t_{pHL} = 1,5 ns$
\vspace{1cm}


\scalebox{2.5}{
\begin{tikztimingtable}
a & 16H4L\\
b & 2L18H \\
x & 4L15H1L\\
y & 6L13H1L\\
z & 8L11H1L\\
\extracode
\begin{pgfonlayer}{background} 
\begin{scope}[semitransparent ,semithick]
%\vertlines[red]{2.1,4.1,...,10.1}
%\vertlines[blue]{3.1,5.1,...,10.1} 
\vertlines[blue]{2,4,...,20} 
\horlines[very thin]{3,4,5}
\end{scope}
% Draw the ruler 
\draw[->] (all rows.south west) ++(down:0.7) node (rulerbegin) {} -- (all rows.south east |- rulerbegin)  -- ++(7mm,0) node[anchor=north] {\small t/ns};
\draw
(rulerbegin)
\foreach \xtext in {1,2,...,9}{
++(2,0) node[anchor=north] {\small \xtext}};
\end{pgfonlayer}
\end{tikztimingtable}
}%scalebox

\end{frame}

\begin{frame}
\frametitle{Verzögerung C}

\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]
\draw (0,1) node[or gate] (g0) {};
\draw (2,0) node[and gate] (g1) {};
\draw (g0.input 1) -- ++(left:1cm) node[anchor=east] {a};
\draw (g0.input 2) -- ++(left:1cm) node[anchor=east] {b};
\draw (g0.output) -- ++(right:3mm) |- node[anchor=east] {x} (g1.input 1);
\draw (g1.input 2) -- ++(left:3) node[anchor=east] {c};
\draw (g1.output) -- node[above] {y} ++(right:1) node[not gate,anchor=input] (g2) {};
\draw (g2.output) -- ++(right:1) node[anchor=west] {z};
\end{tikzpicture}
\hspace{1cm}
$t_{pLH} = 1ns,  t_{pHL} = 0,5 ns$


\scalebox{2.5}{
\begin{tikztimingtable}
a & 2L8H10L\\
b & 6L14H \\
c & 14H6L \\
x & 4L16H\\
y & 6L9H5L\\
z & 7H10L3H\\
\extracode
\begin{pgfonlayer}{background} 
\begin{scope}[semitransparent ,semithick]
%\vertlines[red]{2.1,4.1,...,10.1}
%\vertlines[blue]{3.1,5.1,...,10.1} 
\horlines[very thin]{4,5,6}
\vertlines[blue]{2,4,...,20} 
\end{scope}
% Draw the ruler 
\draw[->] (all rows.south west) ++(down:0.7) node (rulerbegin) {} -- (all rows.south east |- rulerbegin)  -- ++(7mm,0) node[anchor=north] {\small t/ns};
\draw
(rulerbegin)
\foreach \xtext in {1,2,...,12}{
++(2,0) node[anchor=north] {\small \xtext}};
\end{pgfonlayer}
\end{tikztimingtable}
}%scalebox

\end{frame}

\begin{frame}
\frametitle{Verzögerung Hazard}

\begin{tikzpicture}[circuit logic IEC, circuit ee IEC]
\draw (0,0) node[not gate] (g0) {};
\draw (2,0.5) node[and gate] (g1) {};
\draw (g0.input) -- ++(left:1cm) -- ++(up:5mm) node[contact] (c) {} |- (g1.input 1);
\draw (c) -- ++(left:1) node[anchor=east] {a};
\draw (g0.output) -- ++(right:3mm) node[below] {x} |- (g1.input 2);
\draw (g1.output) -- ++(right:1) node[anchor=west] {y};
\end{tikzpicture}
\hspace{1cm}
$t_{p,Inv} = 2ns$
$t_{p,And} = 1ns$
\vspace{1cm}

\scalebox{2.5}{
\begin{tikztimingtable}
a & 4H6L12H\\
x & 8L6H8L\\
y & 12L4H4L\\
\extracode
\begin{pgfonlayer}{background} 
\begin{scope}[semitransparent ,semithick]
%\vertlines[red]{2.1,4.1,...,10.1}
%\vertlines[blue]{3.1,5.1,...,10.1} 
\horlines[very thin]{2,3}
\vertlines[blue]{2,4,...,20} 
\end{scope}
% Draw the ruler 
\draw[->] (all rows.south west) ++(down:0.7) node (rulerbegin) {} -- (all rows.south east |- rulerbegin)  -- ++(7mm,0) node[anchor=north] {\small t/ns};
\draw
(rulerbegin)
\foreach \xtext in {1,2,...,8}{
++(2,0) node[anchor=north] {\small \xtext}};
\end{pgfonlayer}
\end{tikztimingtable}
}%scalebox

\end{frame}