From 5129a5a5448012a53cb9ddae1349c2a2c8571339 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Sun, 8 Nov 2026 18:14:54 +0100 Subject: Add KiCad 9 schematic, project libraries and datasheets Schematic (kicad/), one sheet per function as on ULX3S: - power: TLV62569 bucks for +1V1 / +3V3, AP2112K LDO for +2V5 - usb: USB-C with PTC and TVS, CH347F for JTAG and UART - fpga_power, fpga_config, fpga_banks_01/23/67: ECP5 LFE5U-25F caBGA256 (pin compatible with the 45F), quad SPI flash, 50 MHz CLOCK_50, ball assignment as in PINPLAN.md - ethernet: RTL8211F gigabit PHY, HR911130A RJ45, shield via 1M || 1nF 2kV - sdram: 32 MB W9825G6KH-6 - hdmi: TMDS from the FPGA (LVCMOS33D), AC coupled, ESD protected - user_io: SW, KEY (debounced), LEDR, LEDG, HEX0-HEX3 with DE1 names - gpio: two DE1 compatible 2x20 headers (THDB-ADA on GPIO_0), Pmod A/B, ESD arrays - testpoints: bring-up pads, M3 mounting holes All parts have LCSC numbers, MPN and manufacturer for JLCPCB assembly; footprints are cross-checked against the EasyEDA data. Libraries: ECP5 symbols generated from the Lattice pinout CSVs (kipart), CH347F, RTL8211F, SM410561N symbols, HR911130A symbol and footprint from KiCad library merge requests, generator scripts in lib/tools/. Datasheets of all parts except resistors and capacitors in datasheets/ (manufacturer copyright, not covered by the project licenses). --- .gitignore | 21 + .mcp.json | 12 + README.md | 39 +- ...A-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf | Bin 0 -> 2814593 bytes datasheets/FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv | 701 + datasheets/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv | 854 + ...038-2-1-ECP5-and-ECP5-5G-Hardware-Checklist.pdf | Bin 0 -> 753610 bytes datasheets/README.md | 70 + datasheets/amphenol-10029449-001rlf-C428493.pdf | Bin 0 -> 843958 bytes datasheets/arkled-sm410561n-C141368.pdf | Bin 0 -> 294489 bytes datasheets/brightking-smd0805b020tf-C269102.pdf | Bin 0 -> 198737 bytes datasheets/brightking-smd1206b110tft-C269119.pdf | Bin 0 -> 253856 bytes datasheets/cj-2n7002-C8545.pdf | Bin 0 -> 1575038 bytes datasheets/cjt-a2541hwr-2x6p-C5333437.pdf | Bin 0 -> 2740660 bytes datasheets/diodes-ap2112k-2.5-C176945.pdf | Bin 0 -> 755270 bytes datasheets/fh-cmh201209b2r2mt-C394957.pdf | Bin 0 -> 436141 bytes datasheets/hanrun-hr911130A-C54408.pdf | Bin 0 -> 285654 bytes datasheets/hro-type-c-31-m-12-C165948.pdf | Bin 0 -> 118176 bytes datasheets/kds-1c208000bc0r-C57131.pdf | Bin 0 -> 298715 bytes datasheets/kento-kt-0603r-C2286.pdf | Bin 0 -> 610865 bytes datasheets/keystone-5011-C238127.pdf | Bin 0 -> 278293 bytes datasheets/mdd-smf5.0a-C193402.pdf | Bin 0 -> 4056696 bytes datasheets/murata-blm18pg121sn1d-C14709.pdf | Bin 0 -> 302296 bytes datasheets/nexperia-74hc14d-C5605.pdf | Bin 0 -> 276232 bytes datasheets/realtek-rtl8211f-C187932.pdf | Bin 0 -> 684644 bytes datasheets/rocpu-ss-12d07-5-C2857673.pdf | Bin 0 -> 169042 bytes datasheets/sctf-sx3m50.000m20f30tnn-C2901592.pdf | Bin 0 -> 1872913 bytes datasheets/sxn-smnr4020-2.2uh-C135262.pdf | Bin 0 -> 937017 bytes datasheets/techpublic-tpd4e05u06-C2827646.pdf | Bin 0 -> 2615314 bytes datasheets/ti-tlv62569-C141836.pdf | Bin 0 -> 1357133 bytes datasheets/ti-tpd2e2u06-C1972959.pdf | Bin 0 -> 785929 bytes datasheets/wch-ch347-C18221627.pdf | Bin 0 -> 407616 bytes datasheets/winbond-w25q128jvsiq-C97521.pdf | Bin 0 -> 2511637 bytes datasheets/winbond-w9825g6kh-6-C62246.pdf | Bin 0 -> 1292540 bytes datasheets/xfcn-eh254v-12-40p-C5200276.pdf | Bin 0 -> 153441 bytes datasheets/xinglight-xl-1608sygc-06-C965805.pdf | Bin 0 -> 1577978 bytes datasheets/xkb-ts-1187a-b-a-b-C318884.pdf | Bin 0 -> 805305 bytes datasheets/yxc-x322525mob4si-C9006.pdf | Bin 0 -> 507889 bytes kicad/PINPLAN.md | 203 + kicad/README.md | 126 + kicad/eboard.kicad_pro | 462 + kicad/eboard.kicad_sch | 577 + kicad/ethernet.kicad_sch | 14721 +++++++++++++ kicad/fp-lib-table | 4 + kicad/fpga_banks_01.kicad_sch | 4937 +++++ kicad/fpga_banks_23.kicad_sch | 5217 +++++ kicad/fpga_banks_67.kicad_sch | 5217 +++++ kicad/fpga_config.kicad_sch | 8941 ++++++++ kicad/fpga_power.kicad_sch | 10035 +++++++++ kicad/gpio.kicad_sch | 14156 +++++++++++++ kicad/hdmi.kicad_sch | 4477 ++++ kicad/lib/eboard.kicad_sym | 3828 ++++ .../7SegmentLED_0.56in_1Digit_SM410561N.kicad_mod | 277 + .../RJ45_Hanrun_HR911130A_Horizontal.kicad_mod | 473 + kicad/lib/eboard_fpga.kicad_sym | 5004 +++++ .../RJ45_Hanrun_HR911130A_Horizontal.kicad_sym | 2875 +++ kicad/lib/tools/ch347f.csv | 37 + kicad/lib/tools/derive_symbol.py | 74 + kicad/lib/tools/kicad_sym_grid.py | 44 + kicad/lib/tools/lattice2kipart.py | 107 + kicad/lib/tools/make_7seg_fp.py | 77 + kicad/lib/tools/make_eboard_lib.sh | 62 + kicad/lib/tools/make_ecp5_symbol.sh | 37 + kicad/lib/tools/rtl8211f.csv | 49 + kicad/lib/tools/sm410561n.csv | 18 + kicad/power.kicad_sch | 5459 +++++ kicad/sdram.kicad_sch | 4955 +++++ kicad/sym-lib-table | 5 + kicad/testpoints.kicad_sch | 3227 +++ kicad/tools/gen_sch.py | 1721 ++ kicad/usb.kicad_sch | 8189 ++++++++ kicad/user_io.kicad_sch | 20452 +++++++++++++++++++ 72 files changed, 127739 insertions(+), 1 deletion(-) create mode 100644 .gitignore create mode 100644 .mcp.json create mode 100644 datasheets/FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf create mode 100644 datasheets/FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv create mode 100644 datasheets/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv create mode 100644 datasheets/FPGA-TN-02038-2-1-ECP5-and-ECP5-5G-Hardware-Checklist.pdf create mode 100644 datasheets/README.md create mode 100644 datasheets/amphenol-10029449-001rlf-C428493.pdf create mode 100644 datasheets/arkled-sm410561n-C141368.pdf create mode 100644 datasheets/brightking-smd0805b020tf-C269102.pdf create mode 100644 datasheets/brightking-smd1206b110tft-C269119.pdf create mode 100644 datasheets/cj-2n7002-C8545.pdf create mode 100644 datasheets/cjt-a2541hwr-2x6p-C5333437.pdf create mode 100644 datasheets/diodes-ap2112k-2.5-C176945.pdf create mode 100644 datasheets/fh-cmh201209b2r2mt-C394957.pdf create mode 100644 datasheets/hanrun-hr911130A-C54408.pdf create mode 100644 datasheets/hro-type-c-31-m-12-C165948.pdf create mode 100644 datasheets/kds-1c208000bc0r-C57131.pdf create mode 100644 datasheets/kento-kt-0603r-C2286.pdf create mode 100644 datasheets/keystone-5011-C238127.pdf create mode 100644 datasheets/mdd-smf5.0a-C193402.pdf create mode 100644 datasheets/murata-blm18pg121sn1d-C14709.pdf create mode 100644 datasheets/nexperia-74hc14d-C5605.pdf create mode 100644 datasheets/realtek-rtl8211f-C187932.pdf create mode 100644 datasheets/rocpu-ss-12d07-5-C2857673.pdf create mode 100644 datasheets/sctf-sx3m50.000m20f30tnn-C2901592.pdf create mode 100644 datasheets/sxn-smnr4020-2.2uh-C135262.pdf create mode 100644 datasheets/techpublic-tpd4e05u06-C2827646.pdf create mode 100644 datasheets/ti-tlv62569-C141836.pdf create mode 100644 datasheets/ti-tpd2e2u06-C1972959.pdf create mode 100644 datasheets/wch-ch347-C18221627.pdf create mode 100644 datasheets/winbond-w25q128jvsiq-C97521.pdf create mode 100644 datasheets/winbond-w9825g6kh-6-C62246.pdf create mode 100644 datasheets/xfcn-eh254v-12-40p-C5200276.pdf create mode 100644 datasheets/xinglight-xl-1608sygc-06-C965805.pdf create mode 100644 datasheets/xkb-ts-1187a-b-a-b-C318884.pdf create mode 100644 datasheets/yxc-x322525mob4si-C9006.pdf create mode 100644 kicad/PINPLAN.md create mode 100644 kicad/README.md create mode 100644 kicad/eboard.kicad_pro create mode 100644 kicad/eboard.kicad_sch create mode 100644 kicad/ethernet.kicad_sch create mode 100644 kicad/fp-lib-table create mode 100644 kicad/fpga_banks_01.kicad_sch create mode 100644 kicad/fpga_banks_23.kicad_sch create mode 100644 kicad/fpga_banks_67.kicad_sch create mode 100644 kicad/fpga_config.kicad_sch create mode 100644 kicad/fpga_power.kicad_sch create mode 100644 kicad/gpio.kicad_sch create mode 100644 kicad/hdmi.kicad_sch create mode 100644 kicad/lib/eboard.kicad_sym create mode 100644 kicad/lib/eboard.pretty/7SegmentLED_0.56in_1Digit_SM410561N.kicad_mod create mode 100644 kicad/lib/eboard.pretty/RJ45_Hanrun_HR911130A_Horizontal.kicad_mod create mode 100644 kicad/lib/eboard_fpga.kicad_sym create mode 100644 kicad/lib/tools/RJ45_Hanrun_HR911130A_Horizontal.kicad_sym create mode 100644 kicad/lib/tools/ch347f.csv create mode 100755 kicad/lib/tools/derive_symbol.py create mode 100755 kicad/lib/tools/kicad_sym_grid.py create mode 100755 kicad/lib/tools/lattice2kipart.py create mode 100755 kicad/lib/tools/make_7seg_fp.py create mode 100755 kicad/lib/tools/make_eboard_lib.sh create mode 100755 kicad/lib/tools/make_ecp5_symbol.sh create mode 100644 kicad/lib/tools/rtl8211f.csv create mode 100644 kicad/lib/tools/sm410561n.csv create mode 100644 kicad/power.kicad_sch create mode 100644 kicad/sdram.kicad_sch create mode 100644 kicad/sym-lib-table create mode 100644 kicad/testpoints.kicad_sch create mode 100755 kicad/tools/gen_sch.py create mode 100644 kicad/usb.kicad_sch create mode 100644 kicad/user_io.kicad_sch diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..aa2b1bb --- /dev/null +++ b/.gitignore @@ -0,0 +1,21 @@ +# Reference designs cloned for comparison (ULX3S, ButterStick): separate repositories +/ext/ + +# KiCad: backups, autosave, lock files, caches, local view settings +*-backups/ +_autosave-* +*.lck +~*.lck +\#auto_saved_files\# +fp-info-cache +*.kicad_prl + +# KiCad exports for viewing (schematic PDF etc.) +/kicad/*.pdf + +# Python +__pycache__/ +*.pyc + +# Claude Code local settings (permissions of this machine) +.claude/settings.local.json diff --git a/.mcp.json b/.mcp.json new file mode 100644 index 0000000..7c52214 --- /dev/null +++ b/.mcp.json @@ -0,0 +1,12 @@ +{ + "mcpServers": { + "kicad": { + "type": "stdio", + "command": "kicad-mcp-pro", + "args": [], + "env": { + "KICAD_MCP_PROJECT_DIR": "${PWD}/kicad" + } + } + } +} diff --git a/README.md b/README.md index 81f493b..5314a9a 100644 --- a/README.md +++ b/README.md @@ -39,8 +39,45 @@ The board must have expansion port possibilites at least for low speed extensions. With the ECP5 a 40GbE port is not possible as the fpga does not have serdes at 10 Gigabit. +### Tools ### + +The design is made with KiCad 9. The KiCad project is in `kicad/`, see +`kicad/README.md`. The scripts that generate the project symbol libraries +need kipart (`pipx install kipart`). Footprints and symbols are cross-checked +against the JLCPCB/LCSC (EasyEDA) data with easyeda2kicad +(`pipx install easyeda2kicad`). + +Optional: the KiCad MCP server `kicad-mcp-pro` lets an AI assistant such as +Claude Code work with the KiCad project. Install it with pipx: + + sudo apt install pipx + pipx ensurepath # then open a new terminal + pipx install kicad-mcp-pro + +The file `.mcp.json` in the repository root registers the server for this +project, with `kicad/` as the project directory. Start Claude Code in the +repository root so that `${PWD}` points there. + +### Reference designs ### + +eboard builds on ideas from two open ECP5 boards. No files are taken from +them; they served as examples for the circuits. To look at them, clone them +at the given commit (e.g. into `ext/`, which git ignores): + +| Design | Repository | Commit | Used as example for | +|--------|------------|--------|---------------------| +| ULX3S | | `6a92cec6` (2025-04-27) | one sheet per function, power supply (TLV62569), SDRAM, HDMI output with LVCMOS33D, GPIO without series resistors | +| ButterStick | | `0694ddf` (2023-09-19) | gigabit Ethernet (KSZ9031; eboard uses the RTL8211F), USB-C, FPGA core voltage | + + git clone https://github.com/emard/ulx3s.git ext/ulx3s + git -C ext/ulx3s checkout 6a92cec6 + ### License ### The hardware design files are licensed under CERN-OHL-S-2.0. The software under GPL-3.0-or-later. All documents are licensed under -CC-BY-SA-4.0. \ No newline at end of file +CC-BY-SA-4.0. + +Exception: the manufacturer datasheets in `datasheets/` are copyrighted by +their manufacturers and are not covered by these licenses (see +`datasheets/README.md`). \ No newline at end of file diff --git a/datasheets/FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf b/datasheets/FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf new file mode 100644 index 0000000..f790615 Binary files /dev/null and b/datasheets/FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf differ diff --git a/datasheets/FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv b/datasheets/FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv new file mode 100644 index 0000000..2bcc1b0 --- /dev/null +++ b/datasheets/FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv @@ -0,0 +1,701 @@ +# Pin Out For ECP5U-25,,,,,,,,,, +# Revision 1.1 - Include CABGA256 package,,,,,,,,,, +"# Revised Oct. 17, 2017",,,,,,,,,, +# Revision 2.0 - Include TQFP144 package,,,,,,,,,, +"# Revised Sep. 17, 2021",,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +PAD,Pin/Ball Function,Bank,Dual Function,Differential,High Speed,DQS,CABGA381,CSFBGA285,CABGA256,TQFP144 +1,PL2A,7,-,True_OF_PL2B,TRUE,LDQ8,A4,C12,B1,- +2,PL2B,7,-,Comp_OF_PL2A,TRUE,LDQ8,A5,B12,B2,- +3,VSSIO7,-,-,-,-,-,-,-,-,- +4,PL2C,7,-,True_OF_PL2D,-,LDQ8,B5,-,C3,- +5,VCCIO7,-,-,-,-,-,-,-,-,- +6,PL2D,7,-,Comp_OF_PL2C,-,LDQ8,C5,-,D3,- +7,PL5A,7,-,True_OF_PL5B,TRUE,LDQ8,C4,A12,C1,- +8,VCCAUX,-,-,-,-,-,-,-,-,- +9,PL5C,7,-,True_OF_PL5D,-,LDQ8,A3,-,E3,1 +10,PL5B,7,-,Comp_OF_PL5A,TRUE,LDQ8,B4,-,C2,3 +11,VSS,-,-,-,-,-,-,-,-,- +12,PL5D,7,-,Comp_OF_PL5C,-,LDQ8,B3,-,F3,2 +13,PL8A,7,-,True_OF_PL8B,TRUE,LDQS8,E4,D13,D1,4 +14,VCC,-,-,-,-,-,-,-,-,- +15,PL8C,7,-,True_OF_PL8D,-,LDQ8,C3,-,F4,5 +16,PL8B,7,-,Comp_OF_PL8A,TRUE,LDQSN8,D5,C13,E2,6 +17,VSS,-,-,-,-,-,-,-,-,- +18,PL8D,7,-,Comp_OF_PL8C,-,LDQ8,D3,-,F5,7 +19,PL11A,7,-,True_OF_PL11B,TRUE,LDQ8,F4,-,G5,- +20,VSSIO7,-,-,-,-,-,-,-,-,- +21,PL11C,7,-,True_OF_PL11D,-,LDQ8,E5,-,F2,- +22,PL11B,7,-,Comp_OF_PL11A,TRUE,LDQ8,E3,-,G4,- +23,VCCIO7,-,-,-,-,-,-,-,-,9 +24,PL11D,7,-,Comp_OF_PL11C,-,LDQ8,F5,-,E1,- +25,PL14A,7,-,True_OF_PL14B,TRUE,LDQ20,A2,B13,F1,10 +26,VSSIO7,-,-,-,-,-,-,-,-,- +27,PL14C,7,VREF1_7,True_OF_PL14D,-,LDQ20,B2,C15,G3,11 +28,PL14B,7,-,Comp_OF_PL14A,TRUE,LDQ20,B1,A13,G2,12 +29,VCCIO7,-,-,-,-,-,-,-,-,- +30,PL14D,7,-,Comp_OF_PL14C,-,LDQ20,C2,A15,H3,13 +31,PL17A,7,-,True_OF_PL17B,TRUE,LDQ20,C1,D15,H5,- +32,VCCAUX,-,-,-,-,-,-,-,-,- +33,PL17C,7,-,True_OF_PL17D,-,LDQ20,D2,-,J4,- +34,PL17B,7,-,Comp_OF_PL17A,TRUE,LDQ20,D1,D16,H4,- +35,VSS,-,-,-,-,-,-,-,-,- +36,PL17D,7,-,Comp_OF_PL17C,-,LDQ20,E1,-,J5,- +37,PL20A,7,GR_PCLK7_1,True_OF_PL20B,TRUE,LDQS20,H4,B15,G1,- +38,VCC,-,-,-,-,-,-,-,-,- +39,PL20C,7,GR_PCLK7_0,True_OF_PL20D,-,LDQ20,H5,C16,J3,- +40,PL20B,7,-,Comp_OF_PL20A,TRUE,LDQSN20,G5,A16,H2,- +41,VSS,-,-,-,-,-,-,-,-,- +42,PL20D,7,-,Comp_OF_PL20C,-,LDQ20,H3,-,K3,- +43,PL23A,7,PCLKT7_1,True_OF_PL23B,TRUE,LDQ20,G3,A17,J1,- +44,VSSIO7,-,-,-,-,-,-,-,-,- +45,PL23C,7,PCLKT7_0,True_OF_PL23D,-,LDQ20,F2,B18,K1,- +46,PL23B,7,PCLKC7_1,Comp_OF_PL23A,TRUE,LDQ20,F3,B17,J2,- +47,VCCIO7,-,-,-,-,-,-,-,-,- +48,PL23D,7,PCLKC7_0,Comp_OF_PL23C,-,LDQ20,E2,C17,K2,14 +49,PL26A,6,PCLKT6_1,True_OF_PL26B,TRUE,LDQ32,G2,D17,L1,- +50,VSSIO6,-,-,-,-,-,-,-,-,- +51,PL26C,6,PCLKT6_0,True_OF_PL26D,-,LDQ32,H2,D18,M1,- +52,PL26B,6,PCLKC6_1,Comp_OF_PL26A,TRUE,LDQ32,F1,C18,L2,- +53,VCCIO6,-,-,-,-,-,-,-,-,- +54,PL26D,6,PCLKC6_0,Comp_OF_PL26C,-,LDQ32,G1,F18,M2,- +55,PL29A,6,GR_PCLK6_0,True_OF_PL29B,TRUE,LDQ32,J4,F17,K4,- +56,VCCAUX,-,-,-,-,-,-,-,-,- +57,PL29C,6,GR_PCLK6_1,True_OF_PL29D,-,LDQ32,J3,F15,L4,- +58,PL29B,6,-,Comp_OF_PL29A,TRUE,LDQ32,J5,F16,K5,- +59,VSS,-,-,-,-,-,-,-,-,- +60,PL29D,6,-,Comp_OF_PL29C,-,LDQ32,K3,G16,L5,- +61,PL32A,6,-,True_OF_PL32B,TRUE,LDQS32,K2,G18,N1,- +62,VCC,-,-,-,-,-,-,-,-,- +63,PL32C,6,-,True_OF_PL32D,-,LDQ32,H1,-,L3,- +64,PL32B,6,-,Comp_OF_PL32A,TRUE,LDQSN32,J1,H17,P2,18 +65,VSS,-,-,-,-,-,-,-,-,- +66,PL32D,6,-,Comp_OF_PL32C,-,LDQ32,K1,-,M3,- +67,PL35A,6,-,True_OF_PL35B,TRUE,LDQ32,K4,G15,P1,- +68,VSSIO6,-,-,-,-,-,-,-,-,- +69,PL35C,6,-,True_OF_PL35D,-,LDQ32,L4,H16,M4,22 +70,PL35B,6,VREF1_6,Comp_OF_PL35A,TRUE,LDQ32,K5,H15,R1,19 +71,VCCIO6,-,-,-,-,-,-,-,-,- +72,PL35D,6,-,Comp_OF_PL35C,-,LDQ32,L5,J16,N3,23 +73,PL38A,6,-,True_OF_PL38B,TRUE,LDQ44,M4,-,N4,24 +74,VSSIO6,-,-,-,-,-,-,-,-,- +75,PL38C,6,-,True_OF_PL38D,-,LDQ44,N4,J17,R2,- +76,PL38B,6,-,Comp_OF_PL38A,TRUE,LDQ44,N5,-,P3,25 +77,VCCIO6,-,-,-,-,-,-,-,-,- +78,PL38D,6,-,Comp_OF_PL38C,-,LDQ44,P5,H18,T2,- +79,PL41A,6,-,True_OF_PL41B,TRUE,LDQ44,N3,J18,P4,- +80,VCCAUX,-,-,-,-,-,-,-,-,- +81,PL41C,6,-,True_OF_PL41D,-,LDQ44,L3,K16,R4,26 +82,PL41B,6,-,Comp_OF_PL41A,TRUE,LDQ44,M3,K18,R3,- +83,VSS,-,-,-,-,-,-,-,-,- +84,PL41D,6,-,Comp_OF_PL41C,-,LDQ44,L2,K15,T3,27 +85,PL44A,6,-,True_OF_PL44B,TRUE,LDQS44,N2,K17,R5,28 +86,VCC,-,-,-,-,-,-,-,-,- +87,PL44C,6,-,True_OF_PL44D,-,LDQ44,L1,L15,M5,31 +88,PL44B,6,-,Comp_OF_PL44A,TRUE,LDQSN44,M1,L18,T4,30 +89,VSS,-,-,-,-,-,-,-,-,- +90,PL44D,6,-,Comp_OF_PL44C,-,LDQ44,N1,L16,N5,33 +91,PL47A,6,-,True_OF_PL47B,TRUE,LDQ44,P1,-,M6,34 +92,VSSIO6,-,-,-,-,-,-,-,-,32 +93,PL47B,6,-,Comp_OF_PL47A,TRUE,LDQ44,P2,-,N6,35 +94,VCCIO6,-,-,-,-,-,-,-,-,- +95,PL47C,6,LLC_GPLL0T_IN,True_OF_PL47D,-,LDQ44,P3,M16,P6,37 +96,PL47D,6,LLC_GPLL0C_IN,Comp_OF_PL47C,-,LDQ44,P4,M17,P5,- +97,NC,-,-,-,-,-,-,-,-,- +98,NC,-,-,-,-,-,-,-,-,- +99,GND,-,-,-,-,-,-,-,-,- +100,VCC,-,-,-,-,-,-,-,-,- +101,VCC,-,-,-,-,-,-,-,-,- +102,VSS,-,-,-,-,-,-,-,-,- +103,PB4A,8,D7/IO7,True_OF_PB4B,-,-,R1,N15,T6,40 +104,PB6A,8,D5/MISO2/IO5,True_OF_PB6B,-,-,U1,N17,R7,39 +105,VCC,-,-,-,-,-,-,-,-,- +106,PB4B,8,D6/IO6,Comp_OF_PB4A,-,-,T1,N16,R6,44 +107,PB6B,8,D4/MOSI2/IO4,Comp_OF_PB6A,-,-,V1,M18,P7,41 +108,VSS,-,-,-,-,-,-,-,-,- +109,PB9A,8,D3/IO3,True_OF_PB9B,-,-,W1,N18,N7,45 +110,PB11A,8,D1/MISO/IO1,True_OF_PB11B,-,-,V2,T18,T7,46 +111,VSSIO8,-,-,-,-,-,-,-,-,- +112,PB9B,8,D2/IO2,Comp_OF_PB9A,-,-,Y2,R18,M7,- +113,PB11B,8,D0/MOSI/IO0,Comp_OF_PB11A,-,-,W2,U18,T8,47 +114,VCCIO8,-,-,-,-,-,-,-,-,43 +115,PB13A,8,SN/CSN,True_OF_PB13B,-,-,T2,R17,R8,48 +116,PB15A,8,HOLDN/DI/BUSY/CSSPIN/CEN,True_OF_PB15B,-,-,R2,U17,N8,49 +117,VSSIO8,-,-,-,-,-,-,-,-,- +118,PB13B,8,CS1N,Comp_OF_PB13A,-,-,U2,T17,P8,50 +119,PB15B,8,DOUT/CSON,Comp_OF_PB15A,-,-,R3,V17,M8,51 +120,VCCIO8,-,-,-,-,-,-,-,-,- +121,PB18A,8,WRITEN,-,-,-,T3,R16,M9,52 +122,INITN,8,-,-,-,-,V3,V16,T9,55 +123,VCCAUX,-,-,-,-,-,-,-,-,- +124,CCLK,8,MCLK/SCK,-,-,-,U3,U16,N9,54 +125,PROGRAMN,8,-,-,-,-,W3,T15,R9,57 +126,VSS,-,-,-,-,-,-,-,-,- +127,DONE,8,-,-,-,-,Y3,U15,P9,56 +128,CFG_1,8,-,-,-,-,T4,T14,P10,59 +129,VCC,-,-,-,-,-,-,-,-,- +130,CFG_2,8,-,-,-,-,R4,V15,R10,58 +131,CFG_0,8,-,-,-,-,U4,U14,N10,62 +132,VSS,-,-,-,-,-,-,-,-,- +133,TDO,40,-,-,-,-,V4,V14,M10,60 +134,TCK,40,-,-,-,-,T5,U13,T10,63 +135,VSSIO8,-,-,-,-,-,-,-,-,- +136,TDI,40,-,-,-,-,R5,T13,R11,61 +137,TMS,40,-,-,-,-,U5,V13,T11,64 +138,VCCIO8,-,-,-,-,-,-,-,-,- +139,VCC,-,-,-,-,-,-,-,-,- +140,VCC,-,-,-,-,-,-,-,-,- +141,VSS,-,-,-,-,-,-,-,-,- +142,VSS,-,-,-,-,-,-,-,-,- +143,VCC,-,-,-,-,-,-,-,-,- +144,VCC,-,-,-,-,-,-,-,-,- +145,GND,-,-,-,-,-,-,-,-,- +146,GND,-,-,-,-,-,-,-,-,- +147,RESERVED,-,-,-,-,-,W4,V12,-,- +148,GND,-,-,-,-,-,T7,U12,-,- +149,RESERVED,-,-,-,-,-,W5,V11,-,- +150,GND,-,-,-,-,-,-,-,-,- +151,GND,-,-,-,-,-,-,-,-,- +152,GND,-,-,-,-,-,Y5,V9,-,- +153,GND,-,-,-,-,-,-,-,-,- +154,GND,-,-,-,-,-,T8,U8,-,- +155,GND,-,-,-,-,-,Y6,V8,-,- +156,GND,-,-,-,-,-,-,-,-,- +157,GND,-,-,-,-,-,-,-,-,- +158,GND,-,-,-,-,-,Y7,V6,-,- +159,GND,-,-,-,-,-,-,-,-,- +160,GND,-,-,-,-,-,T9,U6,-,- +161,GND,-,-,-,-,-,Y8,V5,-,- +162,GND,-,-,-,-,-,-,-,-,- +163,GND,-,-,-,-,-,-,-,-,- +164,RESERVED,-,-,-,-,-,W8,V3,-,- +165,GND,-,-,-,-,-,T10,T5,-,- +166,RESERVED,-,-,-,-,-,W9,V2,-,- +167,GND,-,-,-,-,-,-,-,-,- +168,GND,-,-,-,-,-,-,-,-,- +169,RESERVED,-,-,-,-,-,W10,-,-,- +170,GND,-,-,-,-,-,-,-,-,- +171,RESERVED,-,-,-,-,-,W11,-,-,- +172,GND,-,-,-,-,-,-,-,-,- +173,GND,-,-,-,-,-,-,-,-,- +174,GND,-,-,-,-,-,Y11,U1,-,- +175,GND,-,-,-,-,-,-,-,-,- +176,GND,-,-,-,-,-,Y12,T1,-,- +177,VCC,-,-,-,-,-,-,-,-,- +178,VSS,-,-,-,-,-,-,-,-,- +179,VCC,-,-,-,-,-,-,-,-,- +180,GND,-,-,-,-,-,-,-,-,- +181,NC,-,-,-,-,-,-,-,-,- +182,NC,-,-,-,-,-,-,-,-,- +183,PR47D,3,LRC_GPLL0C_IN,Comp_OF_PR47C,-,RDQ44,T17,N1,P12,68 +184,PR47C,3,LRC_GPLL0T_IN,True_OF_PR47D,-,RDQ44,U16,M1,P11,69 +185,VCCIO3,-,-,-,-,-,-,-,-,- +186,PR47B,3,-,Comp_OF_PR47A,TRUE,RDQ44,U17,-,N11,67 +187,VSSIO3,-,-,-,-,-,-,-,-,- +188,PR47A,3,-,True_OF_PR47B,TRUE,RDQ44,U18,-,M11,71 +189,PR44D,3,-,Comp_OF_PR44C,-,RDQ44,T18,N2,N12,- +190,VSS,-,-,-,-,-,-,-,-,- +191,PR44B,3,-,Comp_OF_PR44A,TRUE,RDQSN44,R18,L1,T13,- +192,PR44C,3,-,True_OF_PR44D,-,RDQ44,U19,M2,M12,72 +193,VCC,-,-,-,-,-,-,-,-,- +194,PR44A,3,-,True_OF_PR44B,TRUE,RDQS44,T19,K2,R12,- +195,PR41D,3,-,Comp_OF_PR41C,-,RDQ44,U20,K1,T14,73 +196,VSS,-,-,-,-,-,-,-,-,- +197,PR41B,3,-,Comp_OF_PR41A,TRUE,RDQ44,R20,L3,R14,76 +198,PR41C,3,-,True_OF_PR41D,-,RDQ44,T20,K3,R13,74 +199,VCCAUX,-,-,-,-,-,-,-,-,- +200,PR41A,3,-,True_OF_PR41B,TRUE,RDQ44,P20,M3,P13,77 +201,PR38D,3,-,Comp_OF_PR38C,-,RDQ44,P18,N3,T15,- +202,VCCIO3,-,-,-,-,-,-,-,-,- +203,PR38B,3,-,Comp_OF_PR38A,TRUE,RDQ44,N20,L4,P14,- +204,PR38C,3,-,True_OF_PR38D,-,RDQ44,P19,N4,R15,- +205,VSSIO3,-,-,-,-,-,-,-,-,- +206,PR38A,3,-,True_OF_PR38B,TRUE,RDQ44,N19,K4,N13,- +207,PR35D,3,-,Comp_OF_PR35C,-,RDQ32,R17,H1,N14,78 +208,VCCIO3,-,-,-,-,-,-,-,-,- +209,PR35B,3,VREF1_3,Comp_OF_PR35A,TRUE,RDQ32,P16,J1,R16,79 +210,PR35C,3,-,True_OF_PR35D,-,RDQ32,R16,F1,M13,80 +211,VSSIO3,-,-,-,-,-,-,-,-,- +212,PR35A,3,-,True_OF_PR35B,TRUE,RDQ32,N17,J2,P16,81 +213,PR32D,3,-,Comp_OF_PR32C,-,RDQ32,P17,-,M14,82 +214,VSS,-,-,-,-,-,-,-,-,- +215,PR32B,3,-,Comp_OF_PR32A,TRUE,RDQSN32,M17,G1,P15,- +216,PR32C,3,-,True_OF_PR32D,-,RDQ32,N18,-,L14,84 +217,VCC,-,-,-,-,-,-,-,-,- +218,PR32A,3,-,True_OF_PR32B,TRUE,RDQS32,N16,F2,N16,- +219,PR29D,3,-,Comp_OF_PR29C,-,RDQ32,M18,H2,L12,- +220,VSS,-,-,-,-,-,-,-,-,- +221,PR29B,3,-,Comp_OF_PR29A,TRUE,RDQ32,L17,G3,K12,- +222,PR29C,3,GR_PCLK3_1,True_OF_PR29D,-,RDQ32,L18,J3,L13,- +223,VCCAUX,-,-,-,-,-,-,-,-,- +224,PR29A,3,GR_PCLK3_0,True_OF_PR29B,TRUE,RDQ32,L16,H3,K13,- +225,PR26D,3,PCLKC3_0,Comp_OF_PR26C,-,RDQ32,M19,F3,M15,- +226,VCCIO3,-,-,-,-,-,-,-,-,- +227,PR26B,3,PCLKC3_1,Comp_OF_PR26A,TRUE,RDQ32,M20,G4,L15,- +228,PR26C,3,PCLKT3_0,True_OF_PR26D,-,RDQ32,L19,F4,M16,- +229,VSSIO3,-,-,-,-,-,-,-,-,- +230,PR26A,3,PCLKT3_1,True_OF_PR26B,TRUE,RDQ32,L20,H4,L16,- +231,PR23D,2,PCLKC2_0,Comp_OF_PR23C,-,RDQ20,K20,D1,K15,88 +232,VCCIO2,-,-,-,-,-,-,-,-,- +233,PR23B,2,PCLKC2_1,Comp_OF_PR23A,TRUE,RDQ20,K19,B1,J15,89 +234,PR23C,2,PCLKT2_0,True_OF_PR23D,-,RDQ20,J20,C1,K16,90 +235,VSSIO2,-,-,-,-,-,-,-,-,- +236,PR23A,2,PCLKT2_1,True_OF_PR23B,TRUE,RDQ20,J19,D2,J16,91 +237,PR20D,2,-,Comp_OF_PR20C,-,RDQ20,K18,-,K14,92 +238,VSS,-,-,-,-,-,-,-,-,- +239,PR20B,2,-,Comp_OF_PR20A,TRUE,RDQSN20,H20,B2,H15,93 +240,PR20C,2,GR_PCLK2_0,True_OF_PR20D,-,RDQ20,J18,A2,J14,94 +241,VCC,-,-,-,-,-,-,-,-,- +242,PR20A,2,GR_PCLK2_1,True_OF_PR20B,TRUE,RDQS20,G19,A3,G16,95 +243,PR17D,2,-,Comp_OF_PR17C,-,RDQ20,G20,-,J12,- +244,VSS,-,-,-,-,-,-,-,-,- +245,PR17B,2,-,Comp_OF_PR17A,TRUE,RDQ20,F19,C2,H13,- +246,PR17C,2,-,True_OF_PR17D,-,RDQ20,F20,-,J13,- +247,VCCAUX,-,-,-,-,-,-,-,-,- +248,PR17A,2,-,True_OF_PR17B,TRUE,RDQ20,E20,D3,H12,- +249,PR14D,2,-,Comp_OF_PR14C,-,RDQ20,E19,C3,H14,- +250,VCCIO2,-,-,-,-,-,-,-,-,- +251,PR14B,2,-,Comp_OF_PR14A,TRUE,RDQ20,D19,C4,G15,97 +252,PR14C,2,VREF1_2,True_OF_PR14D,-,RDQ20,D20,B4,G14,98 +253,VSSIO2,-,-,-,-,-,-,-,-,- +254,PR14A,2,-,True_OF_PR14B,TRUE,RDQ20,C20,D4,F16,99 +255,PR11D,2,-,Comp_OF_PR11C,-,RDQ8,J16,-,E16,- +256,VCCIO2,-,-,-,-,-,-,-,-,100 +257,PR11B,2,-,Comp_OF_PR11A,TRUE,RDQ8,H17,A4,G13,- +258,PR11C,2,-,True_OF_PR11D,-,RDQ8,J17,-,F15,- +259,VSSIO2,-,-,-,-,-,-,-,-,- +260,PR11A,2,-,True_OF_PR11B,TRUE,RDQ8,H18,A6,G12,- +261,PR8D,2,-,Comp_OF_PR8C,-,RDQ8,H16,-,F12,102 +262,VSS,-,-,-,-,-,-,-,-,- +263,PR8B,2,-,Comp_OF_PR8A,TRUE,RDQSN8,G18,A7,E15,103 +264,PR8C,2,-,True_OF_PR8D,-,RDQ8,G16,-,F13,104 +265,VCC,-,-,-,-,-,-,-,-,- +266,PR8A,2,-,True_OF_PR8B,TRUE,RDQS8,F17,B6,D16,105 +267,PR5D,2,-,Comp_OF_PR5C,-,RDQ8,F18,-,F14,- +268,VSS,-,-,-,-,-,-,-,-,- +269,PR5B,2,-,Comp_OF_PR5A,TRUE,RDQ8,E17,C6,C15,- +270,PR5C,2,-,True_OF_PR5D,-,RDQ8,E18,-,E14,- +271,VCCAUX,-,-,-,-,-,-,-,-,- +272,PR5A,2,-,True_OF_PR5B,TRUE,RDQ8,D18,D6,C16,- +273,PR2D,2,-,Comp_OF_PR2C,-,RDQ8,F16,-,D14,106 +274,VCCIO2,-,-,-,-,-,-,-,-,- +275,PR2C,2,-,True_OF_PR2D,-,RDQ8,E16,-,C14,107 +276,VSSIO2,-,-,-,-,-,-,-,-,- +277,PR2B,2,S0_IN,Comp_OF_PR2A,TRUE,RDQ8,D17,B7,B15,108 +278,PR2A,2,-,True_OF_PR2B,TRUE,RDQ8,C18,C7,B16,- +279,GND,-,-,-,-,-,-,-,-,- +280,VCC,-,-,-,-,-,-,-,-,- +281,VSS,-,-,-,-,-,-,-,-,- +282,VCC,-,-,-,-,-,-,-,-,- +283,PT67B,1,-,Comp_OF_PT67A,-,-,B20,C8,A15,- +284,VCCIO1,-,-,-,-,-,-,-,-,- +285,PT65B,1,-,Comp_OF_PT65A,-,-,B19,-,A14,- +286,PT67A,1,-,True_OF_PT67B,-,-,A19,B8,B14,110 +287,VSSIO1,-,-,-,-,-,-,-,-,- +288,PT65A,1,-,True_OF_PT65B,-,-,A18,-,A13,- +289,PT62B,1,-,Comp_OF_PT62A,-,-,B18,-,E13,111 +290,VSS,-,-,-,-,-,-,-,-,- +291,PT60B,1,-,Comp_OF_PT60A,-,-,C17,-,C13,113 +292,PT62A,1,-,True_OF_PT62B,-,-,A17,-,D13,112 +293,VCC,-,-,-,-,-,-,-,-,- +294,PT60A,1,-,True_OF_PT60B,-,-,B17,-,B13,114 +295,PT58B,1,-,Comp_OF_PT58A,-,-,D16,-,E12,115 +296,VSS,-,-,-,-,-,-,-,-,- +297,PT56B,1,-,Comp_OF_PT56A,-,-,B16,-,C12,117 +298,PT58A,1,-,True_OF_PT58B,-,-,C16,-,D12,116 +299,VCCAUX,-,-,-,-,-,-,-,-,- +300,PT56A,1,-,True_OF_PT56B,-,-,A16,-,B12,118 +301,PT53B,1,-,Comp_OF_PT53A,-,-,E15,-,A12,119 +302,VCCIO1,-,-,-,-,-,-,-,-,- +303,PT51B,1,-,Comp_OF_PT51A,-,-,C15,-,E11,- +304,PT53A,1,-,True_OF_PT53B,-,-,D15,-,A11,120 +305,VSSIO1,-,-,-,-,-,-,-,-,- +306,PT51A,1,-,True_OF_PT51B,-,-,B15,-,D11,121 +307,PT49B,1,-,Comp_OF_PT49A,-,-,E14,-,C11,- +308,VCCIO1,-,-,-,-,-,-,-,-,122 +309,PT47B,1,-,Comp_OF_PT47A,-,-,C14,-,E10,- +310,PT49A,1,-,True_OF_PT49B,-,-,D14,-,B11,- +311,VSSIO1,-,-,-,-,-,-,-,-,- +312,PT47A,1,-,True_OF_PT47B,-,-,A14,-,D10,- +313,PT44B,1,-,Comp_OF_PT44A,-,-,E13,-,C10,- +314,VSS,-,-,-,-,-,-,-,-,- +315,PT42B,1,-,Comp_OF_PT42A,-,-,C13,-,A10,124 +316,PT44A,1,-,True_OF_PT44B,-,-,D13,-,B10,- +317,VCC,-,-,-,-,-,-,-,-,- +318,PT42A,1,-,True_OF_PT42B,-,-,B13,-,A9,125 +319,PT40B,1,-,Comp_OF_PT40A,-,-,A13,-,E9,126 +320,VSS,-,-,-,-,-,-,-,-,- +321,PT38B,1,GR_PCLK1_1,Comp_OF_PT38A,-,-,E12,-,C9,- +322,PT40A,1,-,True_OF_PT40B,-,-,A12,-,D9,127 +323,VCCAUX,-,-,-,-,-,-,-,-,- +324,PT38A,1,GR_PCLK1_0,True_OF_PT38B,-,-,D12,-,B9,- +325,PT35B,1,PCLKC1_0,Comp_OF_PT35A,-,-,C12,A8,B8,- +326,VCCIO1,-,-,-,-,-,-,-,-,- +327,PT33B,1,PCLKC1_1,Comp_OF_PT33A,-,-,E11,C9,D8,- +328,PT35A,1,PCLKT1_0,True_OF_PT35B,-,-,B12,A9,C8,- +329,VSSIO1,-,-,-,-,-,-,-,-,- +330,PT33A,1,PCLKT1_1,True_OF_PT33B,-,-,D11,B9,E8,- +331,VSS,-,-,-,-,-,-,-,-,- +332,VCC,-,-,-,-,-,-,-,-,- +333,PT29B,0,PCLKC0_0,Comp_OF_PT29A,-,-,C11,C10,A8,- +334,VCCIO0,-,-,-,-,-,-,-,-,- +335,PT27B,0,PCLKC0_1,Comp_OF_PT27A,-,-,A11,A10,B7,- +336,PT29A,0,PCLKT0_0,True_OF_PT29B,-,-,B11,B10,A7,128 +337,VSSIO0,-,-,-,-,-,-,-,-,- +338,PT27A,0,PCLKT0_1,True_OF_PT27B,-,-,A10,A11,C7,- +339,PT24B,0,GR_PCLK0_0,Comp_OF_PT24A,-,-,B10,-,D7,- +340,VSS,-,-,-,-,-,-,-,-,- +341,PT22B,0,-,Comp_OF_PT22A,-,-,C10,-,B6,- +342,PT24A,0,GR_PCLK0_1,True_OF_PT24B,-,-,A9,-,E7,- +343,VCC,-,-,-,-,-,-,-,-,- +344,PT22A,0,-,True_OF_PT22B,-,-,B9,-,C6,- +345,PT20B,0,-,Comp_OF_PT20A,-,-,E9,-,D6,- +346,VSS,-,-,-,-,-,-,-,-,- +347,PT18B,0,-,Comp_OF_PT18A,-,-,A8,-,A6,- +348,PT20A,0,-,True_OF_PT20B,-,-,D9,-,E6,- +349,VCCAUX,-,-,-,-,-,-,-,-,- +350,PT18A,0,-,True_OF_PT18B,-,-,A7,-,A5,- +351,PT15B,0,-,Comp_OF_PT15A,-,-,B8,-,B5,133 +352,VCCIO0,-,-,-,-,-,-,-,-,- +353,PT13B,0,-,Comp_OF_PT13A,-,-,D8,-,D5,135 +354,PT15A,0,-,True_OF_PT15B,-,-,C8,-,C5,134 +355,VSSIO0,-,-,-,-,-,-,-,-,- +356,PT13A,0,-,True_OF_PT13B,-,-,E8,-,E5,136 +357,PT11B,0,-,Comp_OF_PT11A,-,-,C7,-,B4,- +358,VCCIO0,-,-,-,-,-,-,-,-,137 +359,PT9B,0,-,Comp_OF_PT9A,-,-,D7,-,D4,139 +360,PT11A,0,-,True_OF_PT11B,-,-,C6,-,C4,- +361,VSSIO0,-,-,-,-,-,-,-,-,- +362,PT9A,0,-,True_OF_PT9B,-,-,E7,-,E4,140 +363,PT6B,0,-,Comp_OF_PT6A,-,-,D6,-,A4,141 +364,VSS,-,-,-,-,-,-,-,-,- +365,PT4B,0,-,Comp_OF_PT4A,-,-,B6,C11,B3,142 +366,PT6A,0,-,True_OF_PT6B,-,-,E6,-,A3,143 +367,VCC,-,-,-,-,-,-,-,-,- +368,PT4A,0,-,True_OF_PT4B,-,-,A6,B11,A2,- +369,VSS,-,-,-,-,-,-,-,-,- +370,VCC,-,-,-,-,-,-,-,-,- +371,VCC,-,-,-,-,-,-,-,-,- +372,GND,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,GND,-,-,-,-,-,C19,G2,A16,- +0,GND,-,-,-,-,-,H19,L2,H16,- +0,GND,-,-,-,-,-,R19,B3,T16,- +0,GND,-,-,-,-,-,G17,E5,D15,- +0,GND,-,-,-,-,-,M16,F5,N15,- +0,GND,-,-,-,-,-,G15,K5,T12,- +0,GND,-,-,-,-,-,K15,L5,G10,- +0,GND,-,-,-,-,-,N15,F6,H10,- +0,GND,-,-,-,-,-,B14,G6,J10,- +0,GND,-,-,-,-,-,F14,H6,K10,- +0,GND,-,-,-,-,-,G14,J6,F9,- +0,GND,-,-,-,-,-,J14,K6,H9,- +0,GND,-,-,-,-,-,K14,L6,J9,- +0,GND,-,-,-,-,-,M14,M6,K9,- +0,GND,-,-,-,-,-,N14,E7,F8,- +0,GND,-,-,-,-,-,P14,F7,G8,- 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+0,NC,-,-,-,-,-,-,-,-,109 +0,NC,-,-,-,-,-,-,-,-,144 +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,-,-,-,- diff --git a/datasheets/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv b/datasheets/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv new file mode 100644 index 0000000..ab589d6 --- /dev/null +++ b/datasheets/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv @@ -0,0 +1,854 @@ +# Pin Out For ECP5U-45,,,,,,,,,,, +# Revision 2.0. Added caBGA256 Package,,,,,,,,,,, +"# Revised Mar. 19, 2018",,,,,,,,,,, +# Revision 3.0. Added TQFP144 Package,,,,,,,,,,, +"# Revised Sep 17, 2021",,,,,,,,,,, +,,,,,,,,,,, +,,,,,,,,,,, +,,,,,,,,,,, +PAD,Pin/Ball Function,Bank,Dual Function,Differential,High Speed,DQS,CABGA554,CABGA381,CSFBGA285,CABGA256,TQFP144 +1,NC,-,-,-,-,-,-,-,-,-,- +2,NC,-,-,-,-,-,-,-,-,-,- +3,NC,-,-,-,-,-,-,-,-,-,- +4,NC,-,-,-,-,-,-,-,-,-,- +5,NC,-,-,-,-,-,-,-,-,-,- +6,PL11A,7,ULC_GPLL0T_IN,True_OF_PL11B,TRUE,LDQ17,C2,A4,C12,B1,1 +7,PL11B,7,ULC_GPLL0C_IN,Comp_OF_PL11A,TRUE,LDQ17,C1,A5,B12,B2,2 +8,VSSIO7,-,-,-,-,-,-,-,-,-,- +9,PL11C,7,-,True_OF_PL11D,-,LDQ17,C4,B5,-,C3,3 +10,VCCIO7,-,-,-,-,-,-,-,-,-,- +11,PL11D,7,-,Comp_OF_PL11C,-,LDQ17,C3,C5,-,D3,4 +12,PL14A,7,-,True_OF_PL14B,TRUE,LDQ17,D4,C4,A12,C1,5 +13,VCCAUX,-,-,-,-,-,-,-,-,-,- +14,PL14C,7,-,True_OF_PL14D,-,LDQ17,B1,A3,-,E3,- +15,PL14B,7,-,Comp_OF_PL14A,TRUE,LDQ17,D3,B4,-,C2,6 +16,VSS,-,-,-,-,-,-,-,-,-,- +17,PL14D,7,-,Comp_OF_PL14C,-,LDQ17,B3,B3,-,F3,7 +18,PL17A,7,-,True_OF_PL17B,TRUE,LDQS17,D2,E4,D13,D1,- +19,VCC,-,-,-,-,-,-,-,-,-,- +20,PL17C,7,-,True_OF_PL17D,-,LDQ17,E3,C3,-,F4,- +21,PL17B,7,-,Comp_OF_PL17A,TRUE,LDQSN17,E1,D5,C13,E2,- +22,VSS,-,-,-,-,-,-,-,-,-,- +23,PL17D,7,-,Comp_OF_PL17C,-,LDQ17,D1,D3,-,F5,- +24,PL20A,7,-,True_OF_PL20B,TRUE,LDQ17,F2,F4,-,G5,- +25,VSSIO7,-,-,-,-,-,-,-,-,-,- +26,PL20C,7,-,True_OF_PL20D,-,LDQ17,E4,E5,-,F2,- +27,PL20B,7,-,Comp_OF_PL20A,TRUE,LDQ17,F1,E3,-,G4,- +28,VCCIO7,-,-,-,-,-,-,-,-,-,9 +29,PL20D,7,-,Comp_OF_PL20C,-,LDQ17,F3,F5,-,E1,- +30,PL23A,7,-,True_OF_PL23B,TRUE,LDQ29,F5,A2,B13,F1,- +31,VSSIO7,-,-,-,-,-,-,-,-,-,- +32,PL23C,7,VREF1_7,True_OF_PL23D,-,LDQ29,H5,B2,C15,G3,10 +33,PL23B,7,-,Comp_OF_PL23A,TRUE,LDQ29,F4,B1,A13,G2,- +34,VCCIO7,-,-,-,-,-,-,-,-,-,- +35,PL23D,7,-,Comp_OF_PL23C,-,LDQ29,H6,C2,A15,H3,- +36,PL26A,7,-,True_OF_PL26B,TRUE,LDQ29,J6,C1,D15,H5,- +37,VCCAUX,-,-,-,-,-,-,-,-,-,- +38,PL26C,7,-,True_OF_PL26D,-,LDQ29,H4,D2,-,J4,- +39,PL26B,7,-,Comp_OF_PL26A,TRUE,LDQ29,K6,D1,D16,H4,- +40,VSS,-,-,-,-,-,-,-,-,-,- +41,PL26D,7,-,Comp_OF_PL26C,-,LDQ29,L5,E1,-,J5,- +42,PL29A,7,GR_PCLK7_1,True_OF_PL29B,TRUE,LDQS29,K5,H4,B15,G1,- +43,VCC,-,-,-,-,-,-,-,-,-,- +44,PL29C,7,GR_PCLK7_0,True_OF_PL29D,-,LDQ29,M6,H5,C16,J3,- +45,PL29B,7,-,Comp_OF_PL29A,TRUE,LDQSN29,J4,G5,A16,H2,- +46,VSS,-,-,-,-,-,-,-,-,-,- +47,PL29D,7,-,Comp_OF_PL29C,-,LDQ29,M4,H3,-,K3,- +48,PL32A,7,PCLKT7_1,True_OF_PL32B,TRUE,LDQ29,K4,G3,A17,J1,11 +49,VSSIO7,-,-,-,-,-,-,-,-,-,- +50,PL32C,7,PCLKT7_0,True_OF_PL32D,-,LDQ29,N6,F2,B18,K1,12 +51,PL32B,7,PCLKC7_1,Comp_OF_PL32A,TRUE,LDQ29,L4,F3,B17,J2,- +52,VCCIO7,-,-,-,-,-,-,-,-,-,- +53,PL32D,7,PCLKC7_0,Comp_OF_PL32C,-,LDQ29,N5,E2,C17,K2,- +54,PL35A,6,PCLKT6_1,True_OF_PL35B,TRUE,LDQ41,H3,G2,D17,L1,13 +55,VSSIO6,-,-,-,-,-,-,-,-,-,- +56,PL35C,6,PCLKT6_0,True_OF_PL35D,-,LDQ41,H2,H2,D18,M1,14 +57,PL35B,6,PCLKC6_1,Comp_OF_PL35A,TRUE,LDQ41,J3,F1,C18,L2,- +58,VCCIO6,-,-,-,-,-,-,-,-,-,- +59,PL35D,6,PCLKC6_0,Comp_OF_PL35C,-,LDQ41,H1,G1,F18,M2,- +60,PL38A,6,GR_PCLK6_0,True_OF_PL38B,TRUE,LDQ41,K2,J4,F17,K4,- +61,VCCAUX,-,-,-,-,-,-,-,-,-,- +62,PL38C,6,GR_PCLK6_1,True_OF_PL38D,-,LDQ41,K3,J3,F15,L4,- +63,PL38B,6,-,Comp_OF_PL38A,TRUE,LDQ41,J1,J5,F16,K5,- +64,VSS,-,-,-,-,-,-,-,-,-,- +65,PL38D,6,-,Comp_OF_PL38C,-,LDQ41,L3,K3,G16,L5,- +66,PL41A,6,-,True_OF_PL41B,TRUE,LDQS41,L2,K2,G18,N1,- +67,VCC,-,-,-,-,-,-,-,-,-,- +68,PL41C,6,-,True_OF_PL41D,-,LDQ41,K1,H1,-,L3,- +69,PL41B,6,-,Comp_OF_PL41A,TRUE,LDQSN41,M1,J1,H17,P2,- +70,VSS,-,-,-,-,-,-,-,-,-,- +71,PL41D,6,-,Comp_OF_PL41C,-,LDQ41,L1,K1,-,M3,- +72,PL44A,6,-,True_OF_PL44B,TRUE,LDQ41,N1,K4,G15,P1,18 +73,VSSIO6,-,-,-,-,-,-,-,-,-,- +74,PL44C,6,-,True_OF_PL44D,-,LDQ41,N3,L4,H16,M4,- +75,PL44B,6,VREF1_6,Comp_OF_PL44A,TRUE,LDQ41,N2,K5,H15,R1,19 +76,VCCIO6,-,-,-,-,-,-,-,-,-,- +77,PL44D,6,-,Comp_OF_PL44C,-,LDQ41,M3,L5,J16,N3,- +78,PL47A,6,-,True_OF_PL47B,TRUE,LDQ53,P4,-,-,-,- +79,VSSIO6,-,-,-,-,-,-,-,-,-,- +80,PL47C,6,-,True_OF_PL47D,-,LDQ53,P6,-,-,-,- +81,PL47B,6,-,Comp_OF_PL47A,TRUE,LDQ53,P5,-,-,-,- +82,VCCIO6,-,-,-,-,-,-,-,-,-,- +83,PL47D,6,-,Comp_OF_PL47C,-,LDQ53,N4,-,-,-,- +84,PL50A,6,-,True_OF_PL50B,TRUE,LDQ53,R4,-,-,-,- +85,VCCAUX,-,-,-,-,-,-,-,-,-,- +86,PL50C,6,-,True_OF_PL50D,-,LDQ53,R6,-,-,-,- +87,PL50B,6,-,Comp_OF_PL50A,TRUE,LDQ53,T5,-,-,-,- +88,VSS,-,-,-,-,-,-,-,-,-,- +89,PL50D,6,-,Comp_OF_PL50C,-,LDQ53,T4,-,-,-,- +90,PL53A,6,-,True_OF_PL53B,TRUE,LDQS53,V4,M5,-,-,- +91,VCC,-,-,-,-,-,-,-,-,-,- +92,PL53C,6,-,True_OF_PL53D,-,LDQ53,U6,-,-,-,- +93,PL53B,6,-,Comp_OF_PL53A,TRUE,LDQSN53,U5,-,-,-,- +94,VSS,-,-,-,-,-,-,-,-,-,- +95,PL53D,6,-,Comp_OF_PL53C,-,LDQ53,U4,-,-,-,- +96,PL56A,6,-,True_OF_PL56B,TRUE,LDQ53,W4,-,-,-,- +97,VSSIO6,-,-,-,-,-,-,-,-,-,- +98,PL56C,6,-,True_OF_PL56D,-,LDQ53,W5,-,-,-,- +99,PL56B,6,-,Comp_OF_PL56A,TRUE,LDQ53,V6,-,-,-,- +100,VCCIO6,-,-,-,-,-,-,-,-,-,- +101,PL56D,6,-,Comp_OF_PL56C,-,LDQ53,W6,-,-,-,22 +102,PL59A,6,-,True_OF_PL59B,TRUE,LDQ65,T3,M4,-,N4,23 +103,VSSIO6,-,-,-,-,-,-,-,-,-,- +104,PL59C,6,-,True_OF_PL59D,-,LDQ65,R3,N4,J17,R2,24 +105,PL59B,6,-,Comp_OF_PL59A,TRUE,LDQ65,U3,N5,-,P3,25 +106,VCCIO6,-,-,-,-,-,-,-,-,-,- +107,PL59D,6,-,Comp_OF_PL59C,-,LDQ65,P3,P5,H18,T2,26 +108,PL62A,6,-,True_OF_PL62B,TRUE,LDQ65,P2,N3,J18,P4,27 +109,VCCAUX,-,-,-,-,-,-,-,-,-,- +110,PL62C,6,-,True_OF_PL62D,-,LDQ65,T2,L3,K16,R4,28 +111,PL62B,6,-,Comp_OF_PL62A,TRUE,LDQ65,P1,M3,K18,R3,- +112,VSS,-,-,-,-,-,-,-,-,-,- +113,PL62D,6,-,Comp_OF_PL62C,-,LDQ65,R1,L2,K15,T3,30 +114,PL65A,6,-,True_OF_PL65B,TRUE,LDQS65,V1,N2,K17,R5,31 +115,VCC,-,-,-,-,-,-,-,-,-,- +116,PL65C,6,-,True_OF_PL65D,-,LDQ65,U1,L1,L15,M5,34 +117,PL65B,6,-,Comp_OF_PL65A,TRUE,LDQSN65,U2,M1,L18,T4,33 +118,VSS,-,-,-,-,-,-,-,-,-,- +119,PL65D,6,-,Comp_OF_PL65C,-,LDQ65,T1,N1,L16,N5,- +120,PL68A,6,-,True_OF_PL68B,TRUE,LDQ65,V3,P1,-,M6,35 +121,VSSIO6,-,-,-,-,-,-,-,-,-,- +122,PL68B,6,-,Comp_OF_PL68A,TRUE,LDQ65,W1,P2,-,N6,37 +123,VCCIO6,-,-,-,-,-,-,-,-,-,- +124,PL68C,6,LLC_GPLL0T_IN,True_OF_PL68D,-,LDQ65,W2,P3,M16,P6,- +125,PL68D,6,LLC_GPLL0C_IN,Comp_OF_PL68C,-,LDQ65,W3,P4,M17,P5,- +126,NC,-,-,-,-,-,-,-,-,-,- +127,NC,-,-,-,-,-,-,-,-,-,- +128,GND,-,-,-,-,-,-,-,-,-,- +129,VCC,-,-,-,-,-,-,-,-,-,- +130,VCC,-,-,-,-,-,-,-,-,-,- +131,VSS,-,-,-,-,-,-,-,-,-,- +132,PB4A,8,D7/IO7,True_OF_PB4B,-,-,AA1,R1,N15,T6,40 +133,PB6A,8,D5/MISO2/IO5,True_OF_PB6B,-,-,AC1,U1,N17,R7,39 +134,VCC,-,-,-,-,-,-,-,-,-,- +135,PB4B,8,D6/IO6,Comp_OF_PB4A,-,-,AB1,T1,N16,R6,44 +136,PB6B,8,D4/MOSI2/IO4,Comp_OF_PB6A,-,-,AD1,V1,M18,P7,41 +137,VSS,-,-,-,-,-,-,-,-,-,- +138,PB9A,8,D3/IO3,True_OF_PB9B,-,-,AE1,W1,N18,N7,45 +139,PB11A,8,D1/MISO/IO1,True_OF_PB11B,-,-,AD2,V2,T18,T7,46 +140,VSSIO8,-,-,-,-,-,-,-,-,-,- +141,PB9B,8,D2/IO2,Comp_OF_PB9A,-,-,AF2,Y2,R18,M7,- +142,PB11B,8,D0/MOSI/IO0,Comp_OF_PB11A,-,-,AE2,W2,U18,T8,47 +143,VCCIO8,-,-,-,-,-,-,-,-,-,43 +144,PB13A,8,SN/CSN,True_OF_PB13B,-,-,AB2,T2,R17,R8,48 +145,PB15A,8,HOLDN/DI/BUSY/CSSPIN/CEN,True_OF_PB15B,-,-,AA2,R2,U17,N8,49 +146,VSSIO8,-,-,-,-,-,-,-,-,-,- +147,PB13B,8,CS1N,Comp_OF_PB13A,-,-,AC2,U2,T17,P8,50 +148,PB15B,8,DOUT/CSON,Comp_OF_PB15A,-,-,AB3,R3,V17,M8,51 +149,VCCIO8,-,-,-,-,-,-,-,-,-,- +150,PB18A,8,WRITEN,-,-,-,AD3,T3,R16,M9,52 +151,INITN,8,-,-,-,-,AF3,V3,V16,T9,55 +152,VCCAUX,-,-,-,-,-,-,-,-,-,- +153,CCLK,8,MCLK/SCK,-,-,-,AE3,U3,U16,N9,54 +154,PROGRAMN,8,-,-,-,-,AB4,W3,T15,R9,57 +155,VSS,-,-,-,-,-,-,-,-,-,- +156,DONE,8,-,-,-,-,AC4,Y3,U15,P9,56 +157,CFG_1,8,-,-,-,-,AE4,T4,T14,P10,59 +158,VCC,-,-,-,-,-,-,-,-,-,- +159,CFG_2,8,-,-,-,-,AD4,R4,V15,R10,58 +160,CFG_0,8,-,-,-,-,AF4,U4,U14,N10,62 +161,VSS,-,-,-,-,-,-,-,-,-,- +162,TDO,40,-,-,-,-,AB5,V4,V14,M10,60 +163,TCK,40,-,-,-,-,AD5,T5,U13,T10,63 +164,VSSIO8,-,-,-,-,-,-,-,-,-,- +165,TDI,40,-,-,-,-,AC5,R5,T13,R11,61 +166,TMS,40,-,-,-,-,AE5,U5,V13,T11,64 +167,VCCIO8,-,-,-,-,-,-,-,-,-,- +168,VCC,-,-,-,-,-,-,-,-,-,- +169,VCC,-,-,-,-,-,-,-,-,-,- +170,VSS,-,-,-,-,-,-,-,-,-,- +171,VSS,-,-,-,-,-,-,-,-,-,- +172,VCC,-,-,-,-,-,-,-,-,-,- +173,VCC,-,-,-,-,-,-,-,-,-,- +174,GND,-,-,-,-,-,-,-,-,-,- +175,GND,-,-,-,-,-,-,-,-,-,- +176,RESERVED,-,-,-,-,-,AD7,W4,V12,-,- +177,GND,-,-,-,-,-,W10,T7,U12,-,- +178,RESERVED,-,-,-,-,-,AD8,W5,V11,-,- +179,GND,-,-,-,-,-,-,-,-,-,- +180,GND,-,-,-,-,-,-,-,-,-,- +181,GND,-,-,-,-,-,AF6,Y5,V9,-,- +182,GND,-,-,-,-,-,-,-,-,-,- +183,GND,-,-,-,-,-,W11,T8,U8,-,- +184,GND,-,-,-,-,-,AF7,Y6,V8,-,- +185,GND,-,-,-,-,-,-,-,-,-,- +186,GND,-,-,-,-,-,-,-,-,-,- +187,GND,-,-,-,-,-,AF9,Y7,V6,-,- +188,GND,-,-,-,-,-,-,-,-,-,- +189,GND,-,-,-,-,-,W12,T9,U6,-,- +190,GND,-,-,-,-,-,AF10,Y8,V5,-,- +191,GND,-,-,-,-,-,-,-,-,-,- +192,GND,-,-,-,-,-,-,-,-,-,- +193,RESERVED,-,-,-,-,-,AD10,W8,V3,-,- +194,GND,-,-,-,-,-,W13,T10,T5,-,- +195,RESERVED,-,-,-,-,-,AD11,W9,V2,-,- +196,GND,-,-,-,-,-,-,-,-,-,- +197,GND,-,-,-,-,-,-,-,-,-,- +198,RESERVED,-,-,-,-,-,AD13,W10,-,-,- +199,GND,-,-,-,-,-,-,-,-,-,- +200,RESERVED,-,-,-,-,-,AD14,W11,-,-,- +201,GND,-,-,-,-,-,-,-,-,-,- +202,GND,-,-,-,-,-,-,-,-,-,- +203,GND,-,-,-,-,-,AF12,Y11,U1,-,- +204,GND,-,-,-,-,-,-,-,-,-,- +205,GND,-,-,-,-,-,AF13,Y12,T1,-,- +206,GND,-,-,-,-,-,-,-,-,-,- +207,GND,-,-,-,-,-,-,-,-,-,- +208,RESERVED,-,-,-,-,-,AD16,W13,-,-,- +209,GND,-,-,-,-,-,W14,T11,-,-,- +210,RESERVED,-,-,-,-,-,AD17,W14,-,-,- +211,GND,-,-,-,-,-,-,-,-,-,- +212,GND,-,-,-,-,-,-,-,-,-,- +213,GND,-,-,-,-,-,AF15,Y14,-,-,- +214,GND,-,-,-,-,-,-,-,-,-,- +215,GND,-,-,-,-,-,W15,T12,-,-,- +216,GND,-,-,-,-,-,AF16,Y15,-,-,- +217,GND,-,-,-,-,-,-,-,-,-,- +218,GND,-,-,-,-,-,-,-,-,-,- +219,GND,-,-,-,-,-,AF18,Y16,-,-,- +220,GND,-,-,-,-,-,-,-,-,-,- +221,GND,-,-,-,-,-,W16,T13,-,-,- +222,GND,-,-,-,-,-,AF19,Y17,-,-,- +223,GND,-,-,-,-,-,-,-,-,-,- +224,GND,-,-,-,-,-,-,-,-,-,- +225,RESERVED,-,-,-,-,-,AD19,W17,-,-,- +226,GND,-,-,-,-,-,W17,T14,-,-,- +227,RESERVED,-,-,-,-,-,AD20,W18,-,-,- +228,GND,-,-,-,-,-,-,-,-,-,- +229,GND,-,-,-,-,-,-,-,-,-,- +230,RESERVED,-,-,-,-,-,AD22,-,-,-,- +231,GND,-,-,-,-,-,-,-,-,-,- +232,RESERVED,-,-,-,-,-,AD23,-,-,-,- +233,GND,-,-,-,-,-,-,-,-,-,- +234,GND,-,-,-,-,-,-,-,-,-,- +235,GND,-,-,-,-,-,AF21,Y19,-,-,- +236,GND,-,-,-,-,-,-,-,-,-,- +237,GND,-,-,-,-,-,AF22,W20,-,-,- +238,GND,-,-,-,-,-,-,-,-,-,- +239,VSS,-,-,-,-,-,-,-,-,-,- +240,VCC,-,-,-,-,-,-,-,-,-,- +241,VCC,-,-,-,-,-,-,-,-,-,- +242,NC,-,-,-,-,-,-,-,-,-,- +243,NC,-,-,-,-,-,-,-,-,-,- +244,PR68D,3,LRC_GPLL0C_IN,Comp_OF_PR68C,-,RDQ65,W24,T17,N1,P12,68 +245,PR68C,3,LRC_GPLL0T_IN,True_OF_PR68D,-,RDQ65,W25,U16,M1,P11,- +246,VCCIO3,-,-,-,-,-,-,-,-,-,- +247,PR68B,3,-,Comp_OF_PR68A,TRUE,RDQ65,W26,U17,-,N11,67 +248,VSSIO3,-,-,-,-,-,-,-,-,-,- +249,PR68A,3,-,True_OF_PR68B,TRUE,RDQ65,V24,U18,-,M11,- +250,PR65D,3,-,Comp_OF_PR65C,-,RDQ65,T26,T18,N2,N12,- +251,VSS,-,-,-,-,-,-,-,-,-,- +252,PR65B,3,-,Comp_OF_PR65A,TRUE,RDQSN65,U25,R18,L1,T13,71 +253,PR65C,3,-,True_OF_PR65D,-,RDQ65,U26,U19,M2,M12,69 +254,VCC,-,-,-,-,-,-,-,-,-,- +255,PR65A,3,-,True_OF_PR65B,TRUE,RDQS65,V26,T19,K2,R12,73 +256,PR62D,3,-,Comp_OF_PR62C,-,RDQ65,R26,U20,K1,T14,- +257,VSS,-,-,-,-,-,-,-,-,-,- +258,PR62B,3,-,Comp_OF_PR62A,TRUE,RDQ65,P26,R20,L3,R14,74 +259,PR62C,3,-,True_OF_PR62D,-,RDQ65,T25,T20,K3,R13,72 +260,VCCAUX,-,-,-,-,-,-,-,-,-,- +261,PR62A,3,-,True_OF_PR62B,TRUE,RDQ65,P25,P20,M3,P13,77 +262,PR59D,3,-,Comp_OF_PR59C,-,RDQ65,P24,P18,N3,T15,76 +263,VCCIO3,-,-,-,-,-,-,-,-,-,- +264,PR59B,3,-,Comp_OF_PR59A,TRUE,RDQ65,U24,N20,L4,P14,79 +265,PR59C,3,-,True_OF_PR59D,-,RDQ65,R24,P19,N4,R15,78 +266,VSSIO3,-,-,-,-,-,-,-,-,-,- +267,PR59A,3,-,True_OF_PR59B,TRUE,RDQ65,T24,N19,K4,N13,80 +268,PR56D,3,-,Comp_OF_PR56C,-,RDQ53,W21,-,-,-,- +269,VCCIO3,-,-,-,-,-,-,-,-,-,- +270,PR56B,3,-,Comp_OF_PR56A,TRUE,RDQ53,V21,-,-,-,81 +271,PR56C,3,-,True_OF_PR56D,-,RDQ53,W22,-,-,-,- +272,VSSIO3,-,-,-,-,-,-,-,-,-,- +273,PR56A,3,-,True_OF_PR56B,TRUE,RDQ53,W23,-,-,-,- +274,PR53D,3,-,Comp_OF_PR53C,-,RDQ53,U23,-,-,-,- +275,VSS,-,-,-,-,-,-,-,-,-,- +276,PR53B,3,-,Comp_OF_PR53A,TRUE,RDQSN53,U22,-,-,-,82 +277,PR53C,3,-,True_OF_PR53D,-,RDQ53,U21,-,-,-,- +278,VCC,-,-,-,-,-,-,-,-,-,- +279,PR53A,3,-,True_OF_PR53B,TRUE,RDQS53,V23,T16,-,-,84 +280,PR50D,3,-,Comp_OF_PR50C,-,RDQ53,T23,-,-,-,- +281,VSS,-,-,-,-,-,-,-,-,-,- +282,PR50B,3,-,Comp_OF_PR50A,TRUE,RDQ53,T22,-,-,-,- +283,PR50C,3,-,True_OF_PR50D,-,RDQ53,R21,-,-,-,- +284,VCCAUX,-,-,-,-,-,-,-,-,-,- +285,PR50A,3,-,True_OF_PR50B,TRUE,RDQ53,R23,-,-,-,- +286,PR47D,3,-,Comp_OF_PR47C,-,RDQ53,N23,-,-,-,- +287,VCCIO3,-,-,-,-,-,-,-,-,-,- +288,PR47B,3,-,Comp_OF_PR47A,TRUE,RDQ53,P22,-,-,-,- +289,PR47C,3,-,True_OF_PR47D,-,RDQ53,P21,-,-,-,- +290,VSSIO3,-,-,-,-,-,-,-,-,-,- +291,PR47A,3,-,True_OF_PR47B,TRUE,RDQ53,P23,-,-,-,- +292,PR44D,3,-,Comp_OF_PR44C,-,RDQ41,M24,R17,H1,N14,- +293,VCCIO3,-,-,-,-,-,-,-,-,-,- +294,PR44B,3,VREF1_3,Comp_OF_PR44A,TRUE,RDQ41,N25,P16,J1,R16,88 +295,PR44C,3,-,True_OF_PR44D,-,RDQ41,N24,R16,F1,M13,89 +296,VSSIO3,-,-,-,-,-,-,-,-,-,- +297,PR44A,3,-,True_OF_PR44B,TRUE,RDQ41,N26,N17,J2,P16,90 +298,PR41D,3,-,Comp_OF_PR41C,-,RDQ41,L26,P17,-,M14,- +299,VSS,-,-,-,-,-,-,-,-,-,- +300,PR41B,3,-,Comp_OF_PR41A,TRUE,RDQSN41,M26,M17,G1,P15,- +301,PR41C,3,-,True_OF_PR41D,-,RDQ41,K26,N18,-,L14,- +302,VCC,-,-,-,-,-,-,-,-,-,- +303,PR41A,3,-,True_OF_PR41B,TRUE,RDQS41,L25,N16,F2,N16,- +304,PR38D,3,-,Comp_OF_PR38C,-,RDQ41,L24,M18,H2,L12,- +305,VSS,-,-,-,-,-,-,-,-,-,- +306,PR38B,3,-,Comp_OF_PR38A,TRUE,RDQ41,J26,L17,G3,K12,- +307,PR38C,3,GR_PCLK3_1,True_OF_PR38D,-,RDQ41,K24,L18,J3,L13,- +308,VCCAUX,-,-,-,-,-,-,-,-,-,- +309,PR38A,3,GR_PCLK3_0,True_OF_PR38B,TRUE,RDQ41,K25,L16,H3,K13,- +310,PR35D,3,PCLKC3_0,Comp_OF_PR35C,-,RDQ41,H26,M19,F3,M15,- +311,VCCIO3,-,-,-,-,-,-,-,-,-,- +312,PR35B,3,PCLKC3_1,Comp_OF_PR35A,TRUE,RDQ41,J24,M20,G4,L15,- +313,PR35C,3,PCLKT3_0,True_OF_PR35D,-,RDQ41,H25,L19,F4,M16,91 +314,VSSIO3,-,-,-,-,-,-,-,-,-,- +315,PR35A,3,PCLKT3_1,True_OF_PR35B,TRUE,RDQ41,H24,L20,H4,L16,92 +316,PR32D,2,PCLKC2_0,Comp_OF_PR32C,-,RDQ29,N22,K20,D1,K15,- +317,VCCIO2,-,-,-,-,-,-,-,-,-,- +318,PR32B,2,PCLKC2_1,Comp_OF_PR32A,TRUE,RDQ29,L23,K19,B1,J15,- +319,PR32C,2,PCLKT2_0,True_OF_PR32D,-,RDQ29,N21,J20,C1,K16,93 +320,VSSIO2,-,-,-,-,-,-,-,-,-,- +321,PR32A,2,PCLKT2_1,True_OF_PR32B,TRUE,RDQ29,K23,J19,D2,J16,94 +322,PR29D,2,-,Comp_OF_PR29C,-,RDQ29,M23,K18,-,K14,- +323,VSS,-,-,-,-,-,-,-,-,-,- +324,PR29B,2,-,Comp_OF_PR29A,TRUE,RDQSN29,J23,H20,B2,H15,- +325,PR29C,2,GR_PCLK2_0,True_OF_PR29D,-,RDQ29,M21,J18,A2,J14,- +326,VCC,-,-,-,-,-,-,-,-,-,- +327,PR29A,2,GR_PCLK2_1,True_OF_PR29B,TRUE,RDQS29,K22,G19,A3,G16,- +328,PR26D,2,-,Comp_OF_PR26C,-,RDQ29,L22,G20,-,J12,- +329,VSS,-,-,-,-,-,-,-,-,-,- +330,PR26B,2,-,Comp_OF_PR26A,TRUE,RDQ29,K21,F19,C2,H13,95 +331,PR26C,2,-,True_OF_PR26D,-,RDQ29,H23,F20,-,J13,- +332,VCCAUX,-,-,-,-,-,-,-,-,-,- +333,PR26A,2,-,True_OF_PR26B,TRUE,RDQ29,J21,E20,D3,H12,- +334,PR23D,2,-,Comp_OF_PR23C,-,RDQ29,H21,E19,C3,H14,- +335,VCCIO2,-,-,-,-,-,-,-,-,-,- +336,PR23B,2,-,Comp_OF_PR23A,TRUE,RDQ29,F23,D19,C4,G15,97 +337,PR23C,2,VREF1_2,True_OF_PR23D,-,RDQ29,H22,D20,B4,G14,98 +338,VSSIO2,-,-,-,-,-,-,-,-,-,- +339,PR23A,2,-,True_OF_PR23B,TRUE,RDQ29,F22,C20,D4,F16,99 +340,PR20D,2,-,Comp_OF_PR20C,-,RDQ17,F24,J16,-,E16,- +341,VCCIO2,-,-,-,-,-,-,-,-,-,100 +342,PR20B,2,-,Comp_OF_PR20A,TRUE,RDQ17,F26,H17,A4,G13,- +343,PR20C,2,-,True_OF_PR20D,-,RDQ17,E23,J17,-,F15,- +344,VSSIO2,-,-,-,-,-,-,-,-,-,- +345,PR20A,2,-,True_OF_PR20B,TRUE,RDQ17,F25,H18,A6,G12,- +346,PR17D,2,-,Comp_OF_PR17C,-,RDQ17,D26,H16,-,F12,- +347,VSS,-,-,-,-,-,-,-,-,-,- +348,PR17B,2,-,Comp_OF_PR17A,TRUE,RDQSN17,E26,G18,A7,E15,- +349,PR17C,2,-,True_OF_PR17D,-,RDQ17,E24,G16,-,F13,- +350,VCC,-,-,-,-,-,-,-,-,-,- +351,PR17A,2,-,True_OF_PR17B,TRUE,RDQS17,D25,F17,B6,D16,- +352,PR14D,2,-,Comp_OF_PR14C,-,RDQ17,B24,F18,-,F14,- +353,VSS,-,-,-,-,-,-,-,-,-,- +354,PR14B,2,-,Comp_OF_PR14A,TRUE,RDQ17,D24,E17,C6,C15,102 +355,PR14C,2,-,True_OF_PR14D,-,RDQ17,B26,E18,-,E14,103 +356,VCCAUX,-,-,-,-,-,-,-,-,-,- +357,PR14A,2,-,True_OF_PR14B,TRUE,RDQ17,D23,D18,D6,C16,104 +358,PR11D,2,-,Comp_OF_PR11C,-,RDQ17,C24,F16,-,D14,105 +359,VCCIO2,-,-,-,-,-,-,-,-,-,- +360,PR11C,2,-,True_OF_PR11D,-,RDQ17,C23,E16,-,C14,106 +361,VSSIO2,-,-,-,-,-,-,-,-,-,- +362,PR11B,2,URC_GPLL0C_IN,Comp_OF_PR11A,TRUE,RDQ17,C26,D17,B7,B15,107 +363,PR11A,2,URC_GPLL0T_IN,True_OF_PR11B,TRUE,RDQ17,C25,C18,C7,B16,108 +364,NC,-,-,-,-,-,-,-,-,-,- +365,NC,-,-,-,-,-,-,-,-,-,- +366,NC,-,-,-,-,-,-,-,-,-,- +367,NC,-,-,-,-,-,-,-,-,-,- +368,NC,-,-,-,-,-,-,-,-,-,- +369,GND,-,-,-,-,-,-,-,-,-,- +370,VCC,-,-,-,-,-,-,-,-,-,- +371,VSS,-,-,-,-,-,-,-,-,-,- +372,VCC,-,-,-,-,-,-,-,-,-,- +373,PT85B,1,URC_GPLL1C_IN,Comp_OF_PT85A,-,-,A25,B20,C8,A15,- +374,VCCIO1,-,-,-,-,-,-,-,-,-,- +375,PT83B,1,-,Comp_OF_PT83A,-,-,B23,B19,-,A14,- +376,PT85A,1,URC_GPLL1T_IN,True_OF_PT85B,-,-,A24,A19,B8,B14,- +377,VSSIO1,-,-,-,-,-,-,-,-,-,- +378,PT83A,1,-,True_OF_PT83B,-,-,A23,A18,-,A13,111 +379,PT80B,1,-,Comp_OF_PT80A,-,-,D22,B18,-,E13,110 +380,VSS,-,-,-,-,-,-,-,-,-,- +381,PT78B,1,-,Comp_OF_PT78A,-,-,E21,C17,-,C13,112 +382,PT80A,1,-,True_OF_PT80B,-,-,C22,A17,-,D13,- +383,VCC,-,-,-,-,-,-,-,-,-,- +384,PT78A,1,-,True_OF_PT78B,-,-,D21,B17,-,B13,113 +385,PT76B,1,-,Comp_OF_PT76A,-,-,C21,D16,-,E12,114 +386,VSS,-,-,-,-,-,-,-,-,-,- +387,PT74B,1,-,Comp_OF_PT74A,-,-,A22,B16,-,C12,116 +388,PT76A,1,-,True_OF_PT76B,-,-,B21,C16,-,D12,115 +389,VCCAUX,-,-,-,-,-,-,-,-,-,- +390,PT74A,1,-,True_OF_PT74B,-,-,A21,A16,-,B12,117 +391,PT71B,1,-,Comp_OF_PT71A,-,-,A19,E15,-,A12,- +392,VCCIO1,-,-,-,-,-,-,-,-,-,- +393,PT69B,1,-,Comp_OF_PT69A,-,-,B19,C15,-,E11,118 +394,PT71A,1,-,True_OF_PT71B,-,-,A18,D15,-,A11,- +395,VSSIO1,-,-,-,-,-,-,-,-,-,- +396,PT69A,1,-,True_OF_PT69B,-,-,C19,B15,-,D11,119 +397,PT67B,1,-,Comp_OF_PT67A,-,-,D19,-,-,-,- +398,VCCIO1,-,-,-,-,-,-,-,-,-,- +399,PT65B,1,-,Comp_OF_PT65A,-,-,D18,-,-,-,- +400,PT67A,1,-,True_OF_PT67B,-,-,E19,A15,-,-,- +401,VSSIO1,-,-,-,-,-,-,-,-,-,- +402,PT65A,1,-,True_OF_PT65B,-,-,C18,-,-,-,- +403,PT62B,1,-,Comp_OF_PT62A,-,-,E17,-,-,-,- +404,VSS,-,-,-,-,-,-,-,-,-,- +405,PT60B,1,-,Comp_OF_PT60A,-,-,C17,-,-,-,120 +406,PT62A,1,-,True_OF_PT62B,-,-,D17,-,-,-,- +407,VCC,-,-,-,-,-,-,-,-,-,- +408,PT60A,1,-,True_OF_PT60B,-,-,B17,-,-,-,121 +409,PT58B,1,-,Comp_OF_PT58A,-,-,A17,E14,-,C11,- +410,VSS,-,-,-,-,-,-,-,-,-,- +411,PT56B,1,-,Comp_OF_PT56A,-,-,C16,C14,-,E10,- +412,PT58A,1,-,True_OF_PT58B,-,-,A16,D14,-,B11,- +413,VCCAUX,-,-,-,-,-,-,-,-,-,- +414,PT56A,1,-,True_OF_PT56B,-,-,B16,A14,-,D10,- +415,PT53B,1,-,Comp_OF_PT53A,-,-,E16,E13,-,C10,- +416,VCCIO1,-,-,-,-,-,-,-,-,-,122 +417,PT51B,1,-,Comp_OF_PT51A,-,-,A15,C13,-,A10,- +418,PT53A,1,-,True_OF_PT53B,-,-,D16,D13,-,B10,- +419,VSSIO1,-,-,-,-,-,-,-,-,-,- +420,PT51A,1,-,True_OF_PT51B,-,-,A14,B13,-,A9,- +421,PT49B,1,-,Comp_OF_PT49A,-,-,B14,A13,-,E9,- +422,VCCIO1,-,-,-,-,-,-,-,-,-,- +423,PT47B,1,GR_PCLK1_1,Comp_OF_PT47A,-,-,C14,E12,-,C9,- +424,PT49A,1,-,True_OF_PT49B,-,-,B13,A12,-,D9,- +425,VSSIO1,-,-,-,-,-,-,-,-,-,- +426,PT47A,1,GR_PCLK1_0,True_OF_PT47B,-,-,C13,D12,-,B9,- +427,PT44B,1,PCLKC1_0,Comp_OF_PT44A,-,-,D14,C12,A8,B8,- +428,VSS,-,-,-,-,-,-,-,-,-,- +429,PT42B,1,PCLKC1_1,Comp_OF_PT42A,-,-,E14,E11,C9,D8,- +430,PT44A,1,PCLKT1_0,True_OF_PT44B,-,-,D13,B12,A9,C8,124 +431,VCC,-,-,-,-,-,-,-,-,-,- +432,PT42A,1,PCLKT1_1,True_OF_PT42B,-,-,E13,D11,B9,E8,125 +433,VSS,-,-,-,-,-,-,-,-,-,- +434,VCC,-,-,-,-,-,-,-,-,-,- +435,PT38B,0,PCLKC0_0,Comp_OF_PT38A,-,-,A13,C11,C10,A8,- +436,VSS,-,-,-,-,-,-,-,-,-,- +437,PT36B,0,PCLKC0_1,Comp_OF_PT36A,-,-,D11,A11,A10,B7,- +438,PT38A,0,PCLKT0_0,True_OF_PT38B,-,-,A12,B11,B10,A7,126 +439,VCCAUX,-,-,-,-,-,-,-,-,-,- +440,PT36A,0,PCLKT0_1,True_OF_PT36B,-,-,E11,A10,A11,C7,127 +441,PT33B,0,GR_PCLK0_0,Comp_OF_PT33A,-,-,B11,B10,-,D7,- +442,VCCIO0,-,-,-,-,-,-,-,-,-,- +443,PT31B,0,-,Comp_OF_PT31A,-,-,A11,C10,-,B6,- +444,PT33A,0,GR_PCLK0_1,True_OF_PT33B,-,-,C11,A9,-,E7,- +445,VSSIO0,-,-,-,-,-,-,-,-,-,- +446,PT31A,0,-,True_OF_PT31B,-,-,A10,B9,-,C6,- +447,PT29B,0,-,Comp_OF_PT29A,-,-,B10,E10,-,-,- +448,VCCIO0,-,-,-,-,-,-,-,-,-,- +449,PT27B,0,-,Comp_OF_PT27A,-,-,D10,-,-,-,128 +450,PT29A,0,-,True_OF_PT29B,-,-,C10,D10,-,-,- +451,VSSIO0,-,-,-,-,-,-,-,-,-,- +452,PT27A,0,-,True_OF_PT27B,-,-,E10,C9,-,-,- +453,PT24B,0,-,Comp_OF_PT24A,-,-,C9,-,-,-,- +454,VSS,-,-,-,-,-,-,-,-,-,- +455,PT22B,0,-,Comp_OF_PT22A,-,-,D8,-,-,-,- +456,PT24A,0,-,True_OF_PT24B,-,-,D9,-,-,-,- +457,VCC,-,-,-,-,-,-,-,-,-,- +458,PT22A,0,-,True_OF_PT22B,-,-,E8,-,-,-,- +459,PT20B,0,-,Comp_OF_PT20A,-,-,C8,E9,-,D6,- +460,VSS,-,-,-,-,-,-,-,-,-,131 +461,PT18B,0,-,Comp_OF_PT18A,-,-,A9,A8,-,A6,- +462,PT20A,0,-,True_OF_PT20B,-,-,B8,D9,-,E6,133 +463,VCCAUX,-,-,-,-,-,-,-,-,-,- +464,PT18A,0,-,True_OF_PT18B,-,-,A8,A7,-,A5,134 +465,PT15B,0,-,Comp_OF_PT15A,-,-,A6,B8,-,B5,- +466,VCCIO0,-,-,-,-,-,-,-,-,-,- +467,PT13B,0,-,Comp_OF_PT13A,-,-,B6,D8,-,D5,135 +468,PT15A,0,-,True_OF_PT15B,-,-,A5,C8,-,C5,- +469,VSSIO0,-,-,-,-,-,-,-,-,-,- +470,PT13A,0,-,True_OF_PT13B,-,-,C6,E8,-,E5,136 +471,PT11B,0,-,Comp_OF_PT11A,-,-,D6,C7,-,B4,- +472,VCCIO0,-,-,-,-,-,-,-,-,-,137 +473,PT9B,0,-,Comp_OF_PT9A,-,-,C5,D7,-,D4,139 +474,PT11A,0,-,True_OF_PT11B,-,-,E6,C6,-,C4,- +475,VSSIO0,-,-,-,-,-,-,-,-,-,138 +476,PT9A,0,-,True_OF_PT9B,-,-,D5,E7,-,E4,140 +477,PT6B,0,-,Comp_OF_PT6A,-,-,A4,D6,-,A4,142 +478,VSS,-,-,-,-,-,-,-,-,-,- +479,PT4B,0,ULC_GPLL1C_IN,Comp_OF_PT4A,-,-,A3,B6,C11,B3,141 +480,PT6A,0,-,True_OF_PT6B,-,-,B4,E6,-,A3,- +481,VCC,-,-,-,-,-,-,-,-,-,- +482,PT4A,0,ULC_GPLL1T_IN,True_OF_PT4B,-,-,A2,A6,B11,A2,143 +483,VSS,-,-,-,-,-,-,-,-,-,- +484,VCC,-,-,-,-,-,-,-,-,-,- +485,VCC,-,-,-,-,-,-,-,-,-,- +486,GND,-,-,-,-,-,-,-,-,-,- +0,NC,-,-,-,-,-,F19,-,-,-,- +0,GND,-,-,-,-,-,B25,C19,G2,A16,- +0,GND,-,-,-,-,-,E25,H19,L2,H16,- +0,GND,-,-,-,-,-,J25,R19,B3,T16,- +0,GND,-,-,-,-,-,M25,G17,E5,D15,- +0,GND,-,-,-,-,-,R25,M16,F5,N15,- +0,GND,-,-,-,-,-,V25,G15,K5,T12,- +0,GND,-,-,-,-,-,AC25,K15,L5,G10,- +0,GND,-,-,-,-,-,B22,N15,F6,H10,- +0,GND,-,-,-,-,-,E22,B14,G6,J10,- +0,GND,-,-,-,-,-,J22,F14,H6,K10,- +0,GND,-,-,-,-,-,M22,G14,J6,F9,- +0,GND,-,-,-,-,-,R22,J14,K6,H9,- +0,GND,-,-,-,-,-,V22,K14,L6,J9,- +0,GND,-,-,-,-,-,H19,M14,M6,K9,- +0,GND,-,-,-,-,-,B18,N14,E7,F8,- +0,GND,-,-,-,-,-,E18,P14,F7,G8,- +0,GND,-,-,-,-,-,J18,F13,G7,H8,- +0,GND,-,-,-,-,-,K18,G13,H7,J8,- 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The datasheets are +copyrighted by their manufacturers and are **not covered by the project +licenses** (CERN-OHL-S, GPL, CC-BY-SA); they are included unchanged for +convenience. File names: `manufacturer-partname-lcscnumber.pdf`. + +The Lattice pinout CSVs are also read by `kicad/lib/tools/make_ecp5_symbol.sh`. + +The sources below give the current version of each datasheet; check them for +newer revisions. The LCSC links lead to the product page. Where the +manufacturer offers a better (English or newer) version, the manufacturer is +the source. Resistors and capacitors are standard parts (MPN and LCSC number +in the schematic) and not listed. + +### FPGA (Lattice) ### + +Source: [Lattice ECP5 documentation](https://www.latticesemi.com/Products/FPGAandCPLD/ECP5) + +| File | Content | +|------|---------| +| `FPGA-DS-02012-3-4-ECP5-ECP5G-Family-Data-Sheet.pdf` | ECP5/ECP5-5G family data sheet | +| `FPGA-TN-02038-2-1-ECP5-and-ECP5-5G-Hardware-Checklist.pdf` | Hardware checklist (power, configuration, decoupling) | +| `FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv` | Pinout LFE5U-25F | +| `FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv` | Pinout LFE5U-45F | + +Not included because of its size (10 MB): the package diagrams +FPGA-DS-02053 (caBGA256 dimensions), on the same Lattice page. + +The FPGA itself: LFE5U-25F-7BG256I, LCSC [C1550762](https://www.lcsc.com/product-detail/C1550762.html). + +### Parts from the manufacturer ### + +| File | Part | Use | Source | +|------|------|-----|--------| +| `realtek-rtl8211f-C187932.pdf` | Realtek RTL8211F-CG | Gigabit Ethernet PHY | [Realtek](https://www.realtek.com/Product/Index?id=3846) (English version) | +| `wch-ch347-C18221627.pdf` | WCH CH347F | USB to JTAG/UART | [WCH](https://wch-ic.com/products/CH347.html) | +| `ti-tlv62569-C141836.pdf` | TI TLV62569DBVR | Buck converters +1V1, +3V3 | [TI](https://www.ti.com/product/TLV62569) | +| `ti-tpd2e2u06-C1972959.pdf` | TI TPD2E2U06DRLR | USB D+/D- ESD protection | [TI](https://www.ti.com/product/TPD2E2U06) (English; LCSC has the Chinese translation) | + +### Parts from LCSC ### + +| File | Part | Use | LCSC | +|------|------|-----|------| +| `hanrun-hr911130A-C54408.pdf` | HanRun HR911130A | RJ45 with magnetics | [C54408](https://www.lcsc.com/product-detail/C54408.html) | +| `amphenol-10029449-001rlf-C428493.pdf` | Amphenol 10029449-001RLF | HDMI type A connector | [C428493](https://www.lcsc.com/product-detail/C428493.html) | +| `hro-type-c-31-m-12-C165948.pdf` | HRO TYPE-C-31-M-12 | USB-C connector | [C165948](https://www.lcsc.com/product-detail/C165948.html) | +| `xfcn-eh254v-12-40p-C5200276.pdf` | XFCN EH254V-12-40P | GPIO 2x20 box headers | [C5200276](https://www.lcsc.com/product-detail/C5200276.html) | +| `cjt-a2541hwr-2x6p-C5333437.pdf` | CJT A2541HWR-2x6P | Pmod sockets (right angle) | [C5333437](https://www.lcsc.com/product-detail/C5333437.html) | +| `sctf-sx3m50.000m20f30tnn-C2901592.pdf` | SCTF SX3M50.000M20F30TNN | 50 MHz oscillator (CLOCK_50) | [C2901592](https://www.lcsc.com/product-detail/C2901592.html) | +| `kds-1c208000bc0r-C57131.pdf` | KDS 1C208000BC0R (DSX321G) | 8 MHz crystal, CH347 | [C57131](https://www.lcsc.com/product-detail/C57131.html) | +| `yxc-x322525mob4si-C9006.pdf` | YXC X322525MOB4SI | 25 MHz crystal, Ethernet PHY | [C9006](https://www.lcsc.com/product-detail/C9006.html) | +| `rocpu-ss-12d07-5-C2857673.pdf` | ROCPU SS-12D07-5 | Slide switches SW[9:0] | [C2857673](https://www.lcsc.com/product-detail/C2857673.html) | +| `xkb-ts-1187a-b-a-b-C318884.pdf` | XKB TS-1187A-B-A-B | Push buttons KEY[3:0], PROG | [C318884](https://www.lcsc.com/product-detail/C318884.html) | +| `kento-kt-0603r-C2286.pdf` | KENTO KT-0603R | Red LEDs LEDR | [C2286](https://www.lcsc.com/product-detail/C2286.html) | +| `xinglight-xl-1608sygc-06-C965805.pdf` | XINGLIGHT XL-1608SYGC-06 | Yellow-green LEDs (LEDG, status) | [C965805](https://www.lcsc.com/product-detail/C965805.html) | +| `arkled-sm410561n-C141368.pdf` | ARKLED SM410561N | 7-segment displays HEX0-HEX3 | [C141368](https://www.lcsc.com/product-detail/C141368.html) | +| `winbond-w9825g6kh-6-C62246.pdf` | Winbond W9825G6KH-6 | 32 MB SDRAM | [C62246](https://www.lcsc.com/product-detail/C62246.html) | +| `winbond-w25q128jvsiq-C97521.pdf` | Winbond W25Q128JVSIQ | 16 MB SPI flash | [C97521](https://www.lcsc.com/product-detail/C97521.html) | +| `diodes-ap2112k-2.5-C176945.pdf` | Diodes AP2112K-2.5TRG1 | LDO +2V5 | [C176945](https://www.lcsc.com/product-detail/C176945.html) | +| `nexperia-74hc14d-C5605.pdf` | Nexperia 74HC14D | KEY debouncing | [C5605](https://www.lcsc.com/product-detail/C5605.html) | +| `cj-2n7002-C8545.pdf` | CJ 2N7002 | DONE LED driver | [C8545](https://www.lcsc.com/product-detail/C8545.html) | +| `techpublic-tpd4e05u06-C2827646.pdf` | TECH PUBLIC TPD4E05U06DQAR | ESD GPIO headers, HDMI | [C2827646](https://www.lcsc.com/product-detail/C2827646.html) | +| `mdd-smf5.0a-C193402.pdf` | MDD SMF5.0A | VBUS TVS diode | [C193402](https://www.lcsc.com/product-detail/C193402.html) | +| `brightking-smd1206b110tft-C269119.pdf` | Brightking SMD1206B110TFT | PTC 1.1 A, USB VBUS | [C269119](https://www.lcsc.com/product-detail/C269119.html) | +| `brightking-smd0805b020tf-C269102.pdf` | Brightking SMD0805B020TF | PTC 200 mA, HDMI +5V | [C269102](https://www.lcsc.com/product-detail/C269102.html) | +| `sxn-smnr4020-2.2uh-C135262.pdf` | SXN SMNR4020-2.2UH | Buck inductors L1, L2 | [C135262](https://www.lcsc.com/product-detail/C135262.html) | +| `fh-cmh201209b2r2mt-C394957.pdf` | FH CMH201209B2R2MT | PHY 1.0 V inductor | [C394957](https://www.lcsc.com/product-detail/C394957.html) | +| `murata-blm18pg121sn1d-C14709.pdf` | Murata BLM18PG121SN1D | Ferrite beads | [C14709](https://www.lcsc.com/product-detail/C14709.html) | +| `keystone-5011-C238127.pdf` | Keystone 5011 | Scope ground loops | [C238127](https://www.lcsc.com/product-detail/C238127.html) | diff --git a/datasheets/amphenol-10029449-001rlf-C428493.pdf b/datasheets/amphenol-10029449-001rlf-C428493.pdf new file mode 100644 index 0000000..e48dfa4 Binary files /dev/null and b/datasheets/amphenol-10029449-001rlf-C428493.pdf differ diff --git a/datasheets/arkled-sm410561n-C141368.pdf b/datasheets/arkled-sm410561n-C141368.pdf new file mode 100644 index 0000000..4e31cde Binary files /dev/null and b/datasheets/arkled-sm410561n-C141368.pdf differ diff --git a/datasheets/brightking-smd0805b020tf-C269102.pdf b/datasheets/brightking-smd0805b020tf-C269102.pdf new file mode 100644 index 0000000..13f7f9a Binary files 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differ diff --git a/kicad/PINPLAN.md b/kicad/PINPLAN.md new file mode 100644 index 0000000..7730a09 --- /dev/null +++ b/kicad/PINPLAN.md @@ -0,0 +1,203 @@ +#### eboard pin plan (draft 4) #### + +Bank-level assignment of the board interfaces to the ECP5 LFE5U-25F/45F in +caBGA256. All banks run at VCCIO = 3.3 V. The ball-level assignment below is +in the schematic (sheets `fpga_banks_*`, bank 8 in `fpga_config`); it is +preliminary and may change within a bank during layout (BGA escape routing). + +### Banks of the caBGA256 package ### + +Top view, ball A1 top left. Source: Lattice pinout CSVs FPGA-SC-02033 (25F) +and FPGA-SC-02034 (45F); both are identical per bank. + +| Bank | Location | I/O | Notes | +|------|--------------------------|-----|----------------------------------------------------| +| 0 | top left (A-E, 2-8) | 24 | 12 A/B pairs, PCLKT0_0 A7, PCLKT0_1 C7 | +| 1 | top right (A-E, 8-15) | 32 | 16 A/B pairs, PCLKT1_0 C8, PCLKT1_1 E8 | +| 2 | right upper (B-K, 12-16) | 32 | true LVDS pairs, PCLKT2_0 K16, PCLKT2_1 J16 | +| 3 | right lower (K-T, 11-16) | 32 | true LVDS pairs, PCLKT3_0 M16, PCLKT3_1 L16 | +| 6 | left lower (K-T, 1-6) | 32 | true LVDS pairs, PCLKT6_0 M1, PCLKT6_1 L1 | +| 7 | left upper (B-K, 1-5) | 32 | true LVDS pairs, PCLKT7_0 K1, PCLKT7_1 J1 | +| 8 | bottom (M-T, 6-9) | 13 | configuration bank; 5 used by the quad SPI flash, 8 free | + +197 user I/O in total, 192 without the flash pins. + +Balls B1 B2 A2 B3 B14 A15 B15 B16 are PLL inputs on the 45F only and plain +I/O on the 25F: no clocks on these balls. + +### Interfaces ### + +| Interface | Pins | Notes | +|-------------------------------|------|----------------------------------------------------| +| `CLOCK_50` | 1 | 50 MHz oscillator | +| SDRAM 32 MB, x16 W9825G6KH-6 (`DRAM_*`) | 39 | DQ 16, ADDR 13, BA 2, DQM 2, CLK, CKE, CS, RAS, CAS, WE | +| Ethernet RTL8211F, RGMII (`ENET_*`) | 16 | GTX_CLK TX_EN TX_DATA0-3, RX_CLK RX_DV RX_DATA0-3, MDC, MDIO, RST_N, INT_N | +| HDMI out (`HDMI_*`) | 8 | 4 TMDS pairs (LVCMOS33D, as ULX3S), 22 nF AC coupling; no DDC/HPD | +| CH347 UART | 2 | `UART_TXD`, `UART_RXD` | +| `SW[9:0]`, `KEY[3:0]` | 14 | | +| `LEDR[9:0]`, `LEDG[5:0]` | 16 | | +| `HEX0[6:0]` ... `HEX3[6:0]` | 28 | segments driven directly, as on the DE1 | +| `GPIO_0[31:0]` | 32 | DE1 40 pin header; pins 37-40 fixed for the THDB-ADA; Pmod A/B share 16 of these pins | +| `GPIO_1[35:0]` | 36 | DE1 40 pin header at the board edge, fully DE1 compatible | +| **Total** | **192** | of 192 available | + +The SPI flash keeps all four data lines (quad SPI), e.g. for running code +from the flash (execute in place, as on the Raspberry Pi Pico). + +Dropped to make it fit: UART1 and the modem lines of the CH347, HDMI DDC/HPD, +and `GPIO_0[35:32]` as FPGA pins (see below). The Pmods are wired in parallel +to `GPIO_0` and cannot be used together with a card on `GPIO_0`. + +### `GPIO_0`: made for the THDB-ADA ### + +`GPIO_0` is fully DE1 compatible except for header pins 37-40, which are +fixed on the board for the THDB-ADA instead of going to the FPGA: + +| Header pin | DE1 name | THDB-ADA signal | On eboard | Effect on the card | +|------------|--------------|-----------------|--------------------------|----------------------------------| +| 37 | `GPIO_0[32]` | POWER_ON | 10k pull-up to 3.3 V | ADC and clock buffer on | +| 38 | `GPIO_0[33]` | ADC_OEB | 10k pull-down | ADC channel B outputs enabled | +| 39 | `GPIO_0[34]` | (not used) | not connected | | +| 40 | `GPIO_0[35]` | ADC_OEA | 10k pull-down | ADC channel A outputs enabled | + +On the THDB-ADA (schematic ada_v11), POWER_ON drives the AD9248 PDWN_A/B and +the clock buffer enables through an inverter (74HC1G04); its 2k pull-up R59 is +not fitted, and OEA/OEB go directly to the AD9248. So the card needs these +levels from the board. ADC power-down and output tri-state are no longer +controlled by the FPGA. Other DE1 cards work on `GPIO_0` if they do not use +header pins 37-40. + +### Assignment ### + +| Bank | Assignment | Used | +|------|----------------------------------------------------------------|------| +| 0 | Ethernet RGMII + MDC/MDIO + RESET/INT (16), HDMI (8) | 24 | +| 1 | `GPIO_0[31:0]` (32), incl. the Pmod pins | 32 | +| 2 | `GPIO_1[31:0]` (32) | 32 | +| 3 | `GPIO_1[35:32]` (4), `HEX0`-`HEX2`, `HEX3[4:0]` (26), `UART_TXD/RXD` (2) | 32 | +| 6 | `CLOCK_50` (M1), SDRAM (7), `SW` (10), `KEY` (4), `LEDR` (10) | 32 | +| 7 | SDRAM (32): DQ[15:0], DQM[1:0], ADDR, CLK | 32 | +| 8 | `LEDG` (6), `HEX3[6:5]` (2) | 8 | + +Rules for the ball assignment: + +- `CLOCK_50` on M1 (PCLKT6_0). +- Ethernet RXC on a PCLK input of bank 0 (A7 = PCLKT0_0); RXD0-3 and + RX_CTL close to it. TXC is generated with an ODDR, any pin. +- HDMI: each TMDS pair on an A/B ball pair of bank 0 (true + complement). +- SDRAM: DQ and DQM together in bank 7, short and equal-length traces. +- DE1 header pins 1 and 3 (`GPIO_x[0]`, `GPIO_x[2]`) on PCLK inputs: + `GPIO_1` on K16 / J16 (bank 2), `GPIO_0` on C8 / E8 (bank 1). On the + THDB-ADA these are the clock inputs `SMA_DAC4` and `OSC_SMA_ADC4`. +- The 8 PLL-only balls of the 45F carry data or user I/O, never clocks. + +DE1 header pinout (both headers): pins 1-10 = `GPIO_x[0..9]`, 11 = 5 V, +12 = GND, 13-28 = `GPIO_x[10..25]`, 29 = 3.3 V, 30 = GND, +31-40 = `GPIO_x[26..35]`. **On eboard pin 11 carries 3.3 V instead of 5 V**: +there is no 5 V on the headers (the THDB-ADA does not use pin 11). + +The 68 FPGA lines of both headers are connected directly (as on ULX3S) and +protected by 17 TPD4E05U06 ESD arrays (4 lines each, 0.3 pF) at the headers. +Pmod A (GPIO_0_0..7) and Pmod B (GPIO_0_8..15): 2x6 right angle sockets. + +### THDB-ADA on `GPIO_0` + `GPIO_1` ### + +The THDB-ADA (Terasic AD/DA card: AD9248 dual 14 bit ADC, AD9767 dual 14 bit +DAC) uses 35 of the 36 I/O of each header: + +- `GPIO_0` (J7): ADC A/B data, OTRA/OTRB, ADC clocks A/B, OEA/OEB, POWER_ON. +- `GPIO_1` (J8): DAC A/B data, WRTA/WRTB, DAC clocks A/B, DAC_MODE, clock + inputs `SMA_DAC4` (pin 1) and `OSC_SMA_ADC4` (pin 3). + +Sources: THDB-ADA User Manual (Terasic, October 2015), section 3.3; +THDB-ADA schematic ada_v11. + +### Mechanics of the GPIO headers ### + +Coordinates in mm, origin at the bottom left board corner, y up, as in the +DE1 outline drawing (DE1 CD-ROM, `DE1_schematics/DE1_outline.pdf`). + +DE1 board: 152.146 x 152.146 mm, mounting holes 3 mm at (4.191, 4.191), +(4.191, 32.385), (4.191, 147.955), (147.955, 4.191), (147.955, 32.385), +(147.955, 147.955). **eboard uses the same outline and mounting holes.** + +| Header | Pin 1 (square pad) | Orientation | +|------------------|--------------------|-----------------------------------------------| +| JP1 = `GPIO_0` | (125.603, 118.745) | vertical, pin 2 at x + 2.54, pins 39/40 at y = 70.485 | +| JP2 = `GPIO_1` | (145.923, 118.745) | same; 20.32 mm (0.8") right of JP1, 6.22 mm from the right edge | + +Both are 2x20 box headers, 2.54 mm pitch, keying notch on the left side. + +THDB-ADA outline, derived from the photo in Figure 1-2 of the THDB-ADA user +manual (rotated by 180 degrees into the mounted position, scale from the +header pitch, accuracy about +-1 mm). The card is 87.6 x 76.1 mm and sticks out +49 mm beyond the right board edge: + +| Part of the card | x | y | +|-------------------------------------|---------------|---------------| +| strip left of and under JP1 | 113.7 - 132.3 | 57.1 - 133.2 | +| middle part (both headers) | 132.3 - 182.8 | 66.3 - 123.2 | +| outer tabs (outside the board) | 182.8 - 201.3 | 57.1 - 133.2 | +| mounting holes over the board | (119.3, 60.4), (118.7, 129.0) | | + +Keep-out on eboard under the plugged-in card (2 mm margin), polygon: +(111.7, 55.1) - (134.3, 55.1) - (134.3, 64.3) - (152.1, 64.3) - +(152.1, 125.2) - (134.3, 125.2) - (134.3, 135.2) - (111.7, 135.2). +Inside: only low SMD parts (no connectors, buttons, electrolytic capacitors, +displays), and keep about 8 mm around the two card mounting holes free for +spacers. To be checked against a real card (outline, hole positions and the +stack height above the board) before the layout is fixed. + +### Board placement (top view) ### + +``` + +-----------------------------------------------------------------+ + | USB-C HDMI RJ45 Pmod A Pmod B | + | CH347 RTL8211F | + | bank 0 bank 1 GPIO_0 GPIO_1 + | SDRAM +---------------------+ :: :: + | bank 7 | | bank 2 :: :: + | | ECP5 BG256 | :: :: + | bank 6 | | bank 3 :: :: + | +---------------------+ | + | 50 MHz bank 8: flash | + | | + | LEDR[9:0] LEDG[5:0] HEX3 HEX2 HEX1 HEX0 | + | SW[9:0] KEY[3:0] | + +-----------------------------------------------------------------+ +``` + +Test points: two scope ground loops (Keystone 5011, TP6/TP7, GPIO sheet) for +the students' crocodile clips, one next to the GPIO headers and one next to +the Pmods, both outside the THDB-ADA keep-out. Bring-up and production test +use round 1.5 mm top-layer pads (no part): +5V, +3V3, +2V5, +1V1, 4x GND, +VBUS, ETH_1V0, CLOCK_50, UART_TXD/RXD, FPGA_PROGRAMN/INITN/DONE. + +The connectors sit on the top edge, the user I/O on the bottom edge and both +GPIO headers on the right edge (as on the DE1), with `GPIO_1` at the board +edge. The SDRAM sits left of the FPGA. + +### Ball assignment (preliminary) ### + +GPIO pairs: header neighbours `GPIO_x[2k]` / `GPIO_x[2k+1]` sit on the true / +complement ball of one pair (true LVDS pairs in bank 2 and 3), so adjacent +header pins can be used as a differential pair. + +| Bank | Net and ball | +|------|--------------| +| 0 | `ENET_GTX_CLK` D7, `ENET_INT_N` C5, `ENET_MDC` D4, `ENET_MDIO` E4, `ENET_RST_N` B5, `ENET_RX_CLK` A7, `ENET_RX_DATA0` B7, `ENET_RX_DATA1` C7, `ENET_RX_DATA2` B6, `ENET_RX_DATA3` C6, `ENET_RX_DV` A8, `ENET_TX_DATA0` D6, `ENET_TX_DATA1` E6, `ENET_TX_DATA2` D5, `ENET_TX_DATA3` E5, `ENET_TX_EN` E7, `HDMI_CLK_N` A6, `HDMI_CLK_P` A5, `HDMI_D0_N` B4, `HDMI_D0_P` C4, `HDMI_D1_N` A4, `HDMI_D1_P` A3, `HDMI_D2_N` B3, `HDMI_D2_P` A2 | +| 1 | `GPIO_0_0` C8, `GPIO_0_1` B8, `GPIO_0_2` E8, `GPIO_0_3` D8, `GPIO_0_4` B9, `GPIO_0_5` C9, `GPIO_0_6` D9, `GPIO_0_7` E9, `GPIO_0_8` A9, `GPIO_0_9` A10, `GPIO_0_10` B10, `GPIO_0_11` C10, `GPIO_0_12` D10, `GPIO_0_13` E10, `GPIO_0_14` B11, `GPIO_0_15` C11, `GPIO_0_16` D11, `GPIO_0_17` E11, `GPIO_0_18` A11, `GPIO_0_19` A12, `GPIO_0_20` B12, `GPIO_0_21` C12, `GPIO_0_22` D12, `GPIO_0_23` E12, `GPIO_0_24` B13, `GPIO_0_25` C13, `GPIO_0_26` D13, `GPIO_0_27` E13, `GPIO_0_28` A13, `GPIO_0_29` A14, `GPIO_0_30` B14, `GPIO_0_31` A15 | +| 2 | `GPIO_1_0` K16, `GPIO_1_1` K15, `GPIO_1_2` J16, `GPIO_1_3` J15, `GPIO_1_4` J14, `GPIO_1_5` K14, `GPIO_1_6` G16, `GPIO_1_7` H15, `GPIO_1_8` J13, `GPIO_1_9` J12, `GPIO_1_10` H12, `GPIO_1_11` H13, `GPIO_1_12` G14, `GPIO_1_13` H14, `GPIO_1_14` F16, `GPIO_1_15` G15, `GPIO_1_16` F15, `GPIO_1_17` E16, `GPIO_1_18` G12, `GPIO_1_19` G13, `GPIO_1_20` F13, `GPIO_1_21` F12, `GPIO_1_22` D16, `GPIO_1_23` E15, `GPIO_1_24` E14, `GPIO_1_25` F14, `GPIO_1_26` C16, `GPIO_1_27` C15, `GPIO_1_28` C14, `GPIO_1_29` D14, `GPIO_1_30` B16, `GPIO_1_31` B15 | +| 3 | `GPIO_1_32` L16, `GPIO_1_33` L15, `GPIO_1_34` M16, `GPIO_1_35` M15, `HEX0_0` L13, `HEX0_1` L12, `HEX0_2` L14, `HEX0_3` M14, `HEX0_4` N16, `HEX0_5` P15, `HEX0_6` M13, `HEX1_0` N14, `HEX1_1` P16, `HEX1_2` R16, `HEX1_3` N13, `HEX1_4` T15, `HEX1_5` R15, `HEX1_6` P14, `HEX2_0` P13, `HEX2_1` T14, `HEX2_2` R13, `HEX2_3` R14, `HEX2_4` M12, `HEX2_5` N12, `HEX2_6` R12, `HEX3_0` T13, `HEX3_1` M11, `HEX3_2` P12, `HEX3_3` N11, `HEX3_4` P11, `UART_RXD` K13, `UART_TXD` K12 | +| 6 | `CLOCK_50` M1, `DRAM_BA_0` K4, `DRAM_BA_1` K5, `DRAM_CAS_N` L1, `DRAM_CKE` M2, `DRAM_CS_N` L4, `DRAM_RAS_N` L5, `DRAM_WE_N` L2, `KEY0` M6, `KEY1` N6, `KEY2` P6, `KEY3` P5, `LEDR0` L3, `LEDR1` M3, `LEDR2` N1, `LEDR3` P2, `LEDR4` M4, `LEDR5` P1, `LEDR6` R1, `LEDR7` N3, `LEDR8` N4, `LEDR9` R2, `SW0` P3, `SW1` T2, `SW2` P4, `SW3` R4, `SW4` R3, `SW5` T3, `SW6` R5, `SW7` M5, `SW8` T4, `SW9` N5 | +| 7 | `DRAM_ADDR0` H3, `DRAM_ADDR1` H5, `DRAM_ADDR2` J4, `DRAM_ADDR3` H4, `DRAM_ADDR4` J5, `DRAM_ADDR5` G1, `DRAM_ADDR6` J3, `DRAM_ADDR7` H2, `DRAM_ADDR8` K3, `DRAM_ADDR9` J1, `DRAM_ADDR10` K1, `DRAM_ADDR11` J2, `DRAM_ADDR12` K2, `DRAM_CLK` G2, `DRAM_DQ0` B1, `DRAM_DQ1` B2, `DRAM_DQ2` C3, `DRAM_DQ3` D3, `DRAM_DQ4` C1, `DRAM_DQ5` E3, `DRAM_DQ6` C2, `DRAM_DQ7` F3, `DRAM_DQ8` F4, `DRAM_DQ9` E2, `DRAM_DQ10` F5, `DRAM_DQ11` G5, `DRAM_DQ12` F2, `DRAM_DQ13` G4, `DRAM_DQ14` E1, `DRAM_DQ15` F1, `DRAM_LDQM` D1, `DRAM_UDQM` G3 | +| 8 | `HEX3_5` M8, `HEX3_6` M9, `LEDG0` T6, `LEDG1` R7, `LEDG2` R6, `LEDG3` P7, `LEDG4` R8, `LEDG5` P8 | + +### Open points ### + +- Measure a real THDB-ADA: outline, mounting holes, stack height (the keep-out + above is derived from a photo). +- Layer count for the BGA escape (0.8 mm pitch): ULX3S routes the larger + caBGA381 on 4 layers, so 4 layers should work; to be confirmed in layout. +- No spare FPGA pin. If one is needed later: drive ADC_CLK_A and ADC_CLK_B + (`GPIO_0` pins 19/21) from one FPGA pin, as in the current lab designs. diff --git a/kicad/README.md b/kicad/README.md new file mode 100644 index 0000000..68f3265 --- /dev/null +++ b/kicad/README.md @@ -0,0 +1,126 @@ +#### eboard KiCad design #### + +KiCad 9 project. Top level `eboard.kicad_sch`, one sheet per function +(as on ULX3S): + +| Sheet | Content | +|-------------------------|-------------------------------------------------| +| `power.kicad_sch` | +1V1, +3V3 buck converters, +2V5 LDO | +| `usb.kicad_sch` | USB-C, CH347F (JTAG + UART) | +| `fpga_power.kicad_sch` | ECP5 VCC / VCCAUX / VCCIO decoupling | +| `fpga_config.kicad_sch` | ECP5 configuration, SPI flash, 50 MHz clock | +| `ethernet.kicad_sch` | RTL8211F gigabit PHY, HR911130A RJ45 (A3 sheet) | +| `sdram.kicad_sch` | 32 MB SDRAM Winbond W9825G6KH-6 | +| `hdmi.kicad_sch` | HDMI type A output, TMDS from the FPGA | +| `user_io.kicad_sch` | SW, KEY (debounced), LEDR, LEDG, HEX (A3 sheet) | +| `gpio.kicad_sch` | GPIO_0/GPIO_1 DE1 headers, Pmod A/B, ESD (A3) | +| `fpga_banks_01.kicad_sch` | ECP5 banks 0 (Ethernet, HDMI) and 1 (GPIO_0) | +| `fpga_banks_23.kicad_sch` | ECP5 banks 2 (GPIO_1) and 3 (GPIO_1, HEX, UART) | +| `fpga_banks_67.kicad_sch` | ECP5 banks 6 (clock, SW, KEY, LEDR, SDRAM control) and 7 (SDRAM) | +| `testpoints.kicad_sch` | Test pads (rails, GND, clock, UART), M3 mounting holes H1-H6 (GND) | + +Libraries: + +- `lib/eboard_fpga.kicad_sym`: ECP5 LFE5U-25F/45F caBGA256, generated by + `lib/tools/make_ecp5_symbol.sh` from the Lattice pinout CSVs. +- `lib/eboard.kicad_sym`: CH347F, RTL8211F and SM410561N (kipart CSVs in + `lib/tools/`) plus the HanRun HR911130A symbol, built by + `lib/tools/make_eboard_lib.sh`. +- `lib/eboard.pretty`: HanRun HR911130A footprint, and the footprint of the + ARKLED SM410561N 0.56" 7-segment display (generated by + `lib/tools/make_7seg_fp.py` from the ARKLED specification). + +The generator scripts need Python 3 and +[kipart](https://github.com/devbisme/KiPart), installed with pipx: + + pipx install kipart + kicad/lib/tools/make_ecp5_symbol.sh # -> lib/eboard_fpga.kicad_sym + kicad/lib/tools/make_eboard_lib.sh # -> lib/eboard.kicad_sym + +Both scripts overwrite their library; edit the sources in `lib/tools/` +(kipart CSVs, Lattice pinout CSVs in `datasheets/`, `*.kicad_sym`) instead. +The kipart CSVs `ch347f.csv`, `rtl8211f.csv` and `sm410561n.csv` are transcribed by hand from +the datasheets; every generated symbol has a hidden `Source` field that names +the datasheet tables or the Lattice CSV it was made from. + +Self-made footprints and symbols are cross-checked against the EasyEDA data +that JLCPCB uses for assembly, fetched with +[easyeda2kicad](https://github.com/uPesy/easyeda2kicad.py) into a scratch +directory (not into the project libraries): + + pipx install easyeda2kicad + easyeda2kicad --lcsc_id C141368 --symbol --footprint --output /tmp/ee/ee + +Results (pad positions after aligning the orientation): + +| Part (LCSC) | Project footprint | Max. difference | +|------------------------|-----------------------------------------------------|-----------------| +| SM410561N (C141368) | `eboard:7SegmentLED_0.56in_1Digit_SM410561N` | 0.000 mm, pin assignment identical | +| RTL8211F (C187932) | `QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm_ThermalVias` | 0.04 mm (pad length), EP 3.6 mm in both | +| CH347F (C18221627) | `QFN-28-1EP_4x4mm_P0.4mm_EP2.4x2.4mm_ThermalVias` | 0.06 mm (pad length); EasyEDA EP 2.7 mm, KiCad 2.4 mm | +| HR911130A (C54408) | `eboard:RJ45_Hanrun_HR911130A_Horizontal` | 0.10 mm (EasyEDA offsets the even pins by 1.17 mm instead of 1.27 mm from the datasheet) | +| LFE5U-25F caBGA256 (C1550762) | `BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_...` | 0.000 mm, all 256 balls | +| HDMI 10029449-001RLF (C428493) | `HDMI_A_Amphenol_10029449-x01xLF_Horizontal` | 0.000 mm incl. shell (EasyEDA pad "20" = SH) | +| USB-C TYPE-C-31-M-12 (C165948) | `USB_C_Receptacle_HRO_TYPE-C-31-M-12` | < 0.1 mm; EasyEDA merges A1/B12 etc. into custom pads, shell slots slightly larger | +| Box header EH254V-12-40P (C5200276) | `IDC-Header_2x20_P2.54mm_Vertical` | 0.000 mm | +| Pmod socket A2541HWR-2x6P (C5333437) | `PinSocket_2x06_P2.54mm_Horizontal` | 0.000 mm; drill 1.0 mm (KiCad) vs 1.27 mm (EasyEDA) | +| Slide switch SS-12D07-5 (C2857673) | C&K `SW_Slide_SPDT_Straight_CK_OS102011MS2Q` | 0.000 mm (checked against the ROCPU datasheet) | +| TS-1187A (C318884) | `SW_Push_1P1T_XKB_TS-1187A` | 0.03 mm; EasyEDA numbers the pads 1-4, KiCad 1/1/2/2 (same connected pairs) | +| TPD4E05U06 (C2827646) | `USON-10_2.5x1.0mm_P0.5mm` | 0.015 mm | +| W9825G6KH-6 (C62246) | `TSOP-II-54_22.2x10.16mm_P0.8mm` | 0.11 mm (pad length) | +| SMNR4020-2.2UH (C135262) | `L_Sunlord_SWPA4020S` | 0.30 mm, EasyEDA pads larger; matches the SXN land pattern | +| SMF5.0A (C193402) | `D_SOD-123F` | 0.23 mm, EasyEDA pads further apart | +| all other parts (SOT-23/-5/-553, SOIC, crystals, oscillator, 0402-1206 passives, LEDs, Keystone 5011) | KiCad library | < 0.2 mm (pad length / IPC density) | + +Polarity of LEDs and diodes (pad 1 = cathode) and the part rotations are checked in +the JLCPCB placement preview before ordering. + +The HR911130A symbol and footprint are taken from the open KiCad library merge +requests [kicad-symbols!5505](https://gitlab.com/kicad/libraries/kicad-symbols/-/merge_requests/5505) +(commit 6183ff89) and [kicad-footprints!4647](https://gitlab.com/kicad/libraries/kicad-footprints/-/merge_requests/4647) +(commit 0c65d539), converted from KiCad 10 to KiCad 9 format (version header +changed, KiCad 10 attributes with default values removed). The footprint was +checked against the HanRun datasheet (all pads within 0.005 mm). KiCad library +license: CC-BY-SA 4.0 with the KiCad library exception. Once the merge requests +are in a KiCad release, the project can switch to `Connector:` / +`Connector_RJ:RJ45_Hanrun_HR911130A_Horizontal`. + +The bank assignment of all interfaces is in [PINPLAN.md](PINPLAN.md). + +### Schematic generator (historical) ### + +The first version of the schematic was generated by `tools/gen_sch.py` (part +choices, LCSC/MPN table, ball assignment of the FPGA banks are in the script). +From now on the schematic is edited in KiCad. **Do not run the script again**: +it overwrites all sheets and discards the changes made in KiCad. It is kept to +document how the schematic was created. + +### Net naming ### + +Signals between sheets are global labels. Signals that go to the FPGA use the +names of the Terasic DE1 board, so that DE1 course material and constraint +files can be reused. The net name is also the port name in the LPF. + +| Net | LPF / HDL port | Function | +|-----------------|-----------------|--------------------------------------------| +| `CLOCK_50` | `CLOCK_50` | 50 MHz system clock | +| `SW0` ... `SW9` | `SW[9:0]` | slide switches | +| `KEY0` ... `KEY3` | `KEY[3:0]` | push buttons, active low | +| `LEDR0` ... `LEDR9` | `LEDR[9:0]` | red LEDs, active high | +| `LEDG0` ... `LEDG5` | `LEDG[5:0]` | green LEDs, active high | +| `HEX0_0` ... `HEX3_6` | `HEX0[6:0]` ... `HEX3[6:0]` | 7-segment displays, active low | +| `UART_TXD` | `UART_TXD` | FPGA transmits (to CH347 RXD0) | +| `UART_RXD` | `UART_RXD` | FPGA receives (from CH347 TXD0) | +| `GPIO_0_0` ... `GPIO_0_31` | `GPIO_0[31:0]` | DE1 40 pin header, shared with Pmod A/B; pins 37-40 fixed for the THDB-ADA | +| `GPIO_1_0` ... `GPIO_1_35` | `GPIO_1[35:0]` | DE1 40 pin header at the board edge | +| `DRAM_DQ0` ... `DRAM_DQ15`, `DRAM_ADDR0` ... `DRAM_ADDR12` | `DRAM_DQ[15:0]`, `DRAM_ADDR[12:0]` | SDRAM data and address (DE1 names, ADDR12 added for 32 MB) | +| `DRAM_BA_0`, `DRAM_BA_1`, `DRAM_LDQM`, `DRAM_UDQM`, `DRAM_WE_N`, `DRAM_CAS_N`, `DRAM_RAS_N`, `DRAM_CS_N`, `DRAM_CKE`, `DRAM_CLK` | same | SDRAM control, as on the DE1 | +| `ENET_GTX_CLK`, `ENET_TX_EN`, `ENET_TX_DATA0..3` | `ENET_TX_DATA[3:0]` ... | RGMII transmit, DE2-115 names | +| `ENET_RX_CLK`, `ENET_RX_DV`, `ENET_RX_DATA0..3` | `ENET_RX_DATA[3:0]` ... | RGMII receive | +| `ENET_MDC`, `ENET_MDIO`, `ENET_RST_N`, `ENET_INT_N` | | PHY management, reset (active low, PHY held in reset by a pull-down), interrupt | +| `HDMI_D0_P/N`, `HDMI_D1_P/N`, `HDMI_D2_P/N`, `HDMI_CLK_P/N` | | HDMI TMDS pairs (LVCMOS33D), AC coupled to the connector | +| `JTAG_TCK` ... | | FPGA JTAG, driven by the CH347 | + +Directions are always seen from the FPGA. + +Local nets inside a sheet (e.g. `FLASH_CS`, `FPGA_DONE`) use local labels. diff --git a/kicad/eboard.kicad_pro b/kicad/eboard.kicad_pro new file mode 100644 index 0000000..3896eb7 --- /dev/null +++ b/kicad/eboard.kicad_pro @@ -0,0 +1,462 @@ +{ + "board": { + "3dviewports": [], + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], 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(pts + (xy 342.9 137.16) (xy 342.9 129.54) + ) + (stroke + (width 0) + (type default) + ) + (uuid "b0a4fed9-c82c-5711-8caf-4501387ead93") + ) + (wire + (pts + (xy 340.36 137.16) (xy 340.36 129.54) + ) + (stroke + (width 0) + (type default) + ) + (uuid "9ad11e1b-08cb-57e6-91e5-54f0e3983ae4") + ) + (wire + (pts + (xy 340.36 177.8) (xy 340.36 180.34) + ) + (stroke + (width 0) + (type default) + ) + (uuid "e80f4e9a-2f5d-5fb4-9735-d58c1de0bec7") + ) + (wire + (pts + (xy 340.36 180.34) (xy 325.12 180.34) + ) + (stroke + (width 0) + (type default) + ) + (uuid "1ac5ff57-dd5c-5ad3-83e7-c5728c69dda2") + ) + (wire + (pts + (xy 325.12 180.34) (xy 307.34 180.34) + ) + (stroke + (width 0) + (type default) + ) + (uuid "a472b382-6559-5576-a415-92c307c46478") + ) + (wire + (pts + (xy 378.46 152.4) (xy 378.46 147.32) + ) + (stroke + (width 0) + (type default) + ) + (uuid "956c8915-3d81-5c36-96e2-54a808386a6f") + ) + (wire + (pts + (xy 391.16 152.4) (xy 391.16 147.32) + ) + (stroke + (width 0) + (type default) + ) + (uuid "6396a58e-dad4-5e45-9bff-db3d88b771e8") + ) + (wire + (pts + (xy 365.76 152.4) (xy 365.76 147.32) + ) + (stroke + (width 0) + (type default) + ) + (uuid "ae158601-e62e-54a3-826b-08e8ba5bf098") + ) + (text "RGMII series resistors 22R:\nTX (ENET_GTX_CLK ... ENET_TX_DATA3) close to the FPGA,\nRX (ENET_RX_CLK ... ENET_RX_DATA3) close to the PHY." + (exclude_from_sim no) + (at 30.48 38.1 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "f6c4cd83-c2ce-5811-9911-09bde7f37e44") + ) + (text "PHYAD0 = 1" + (exclude_from_sim no) + (at 30.48 231.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "6e1e5e6c-ebe8-5bf1-b699-3869cac55406") + ) + (text "PHYAD1 = 0" + (exclude_from_sim no) + (at 45.72 228.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "e6a5d71f-0230-5a6a-8453-c85f16de5c68") + ) + (text "PHYAD2 = 0" + (exclude_from_sim no) + (at 60.96 228.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ec35c1ae-89d0-57a4-8b90-3a279bf3d95c") + ) + (text "PLLOFF = 0" + (exclude_from_sim no) + (at 76.2 228.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "f9842c54-3578-5f65-a0c7-fad3ef1e9203") + ) + (text "TXDLY = 1" + (exclude_from_sim no) + (at 91.44 231.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "93eba009-65e0-5991-802e-b7d3450eb567") + ) + (text "RXDLY = 1" + (exclude_from_sim no) + (at 106.68 231.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "79a257dd-018f-52cb-9eb7-1bcbd23cb645") + ) + (text "CFG_EXT = 1" + (exclude_from_sim no) + (at 121.92 231.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "b90dddfe-8968-51b0-99da-c8fac99b7749") + ) + (text "CFG_LDO0 = 0" + (exclude_from_sim no) + (at 137.16 228.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "e2fa8602-44a0-566d-95b8-5f012ba6a384") + ) + (text "CFG_LDO1 = 0" + (exclude_from_sim no) + (at 152.4 228.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "3924ad87-6d6a-597c-811d-6c5174c115b1") + ) + (text "Strap resistors (RTL8211F datasheet 7.8): PHY address 1, 2 ns TXC and RXC delay inside the PHY,\nRGMII I/O at 3.3 V from DVDD_RG (CFG_EXT = 1, CFG_LDO = 00), LED1/LED2 active high." + (exclude_from_sim no) + (at 30.48 182.88 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "202e9358-c6d3-59a3-81ca-1d84fcbdccf8") + ) + (text "ENET_RST_N: 10k pull-down keeps the PHY in reset\nuntil the FPGA drives it high (>= 10 ms low,\nwait 50 ms before MDIO access)." + (exclude_from_sim no) + (at 172.72 233.68 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "943c4bb0-0d75-57f1-86e2-d1967d4a3131") + ) + (text "DVDD33, DVDD_RG" + (exclude_from_sim no) + (at 241.3 41.91 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "2dcc55d5-c431-5ddf-8628-a707d7e28c5e") + ) + (text "AVDD33 (pins 11, 40)" + (exclude_from_sim no) + (at 294.64 41.91 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "12a16bfd-062c-5e3a-950f-7e613fca8d82") + ) + (text "Test pad: PHY 1.0 V" + (exclude_from_sim no) + (at 345.44 60.96 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "f57a51c3-e88d-595f-b7a3-c8e79fbe90b9") + ) + (text "1.0 V core (DVDD10 pin 21, AVDD10 pins 3, 8, 38): only for the PHY.\nInductor Isat > 600 mA, X5R/X7R capacitors." + (exclude_from_sim no) + (at 236.22 96.52 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "968f64b3-07e5-5a71-9304-560e082f2956") + ) + (text "RJ45 with 1000Base-T magnetics. Transformer centre tap via 100 nF to GND\n(voltage-mode PHY, no external MDI termination needed).\nLEDs: green = LED2 (1000 Mbit/s link/activity), yellow = LED1 (100 Mbit/s).\nShield ETH_SHIELD: 1M || 1 nF 2 kV to GND, keeps the 1500 V isolation of the magnetics\nwith shielded cables. Layout: own copper island under the jack shell, >= 2 mm gap to GND." + (exclude_from_sim no) + (at 294.64 198.12 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ffdd7361-9e17-5a24-b05c-bb2335f15095") + ) + (text "Ethernet: RTL8211F gigabit PHY, RGMII to the FPGA bank 0" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "fe6a65d7-131a-57c4-af13-7560499e8ac8") + ) + (text "Net names as on the DE2-115 (ENET_*), seen from the FPGA. RXC (ENET_RX_CLK) goes to a PCLK pin (A7).\n3.3 V rise time must be >= 0.5 ms (TLV62569 soft start: 0.8 ms)." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "3cde1cf0-fdba-54fd-81f0-3b84dd443ae7") + ) + (label "PHY_TXC" + (at 152.4 124.46 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "e0c413cb-0b88-567d-bb20-36b3f29b4bca") + ) + (label "PHY_TXCTL" + (at 152.4 127 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "44066b06-8749-5842-8b91-8bc8b736fb64") + ) + (label "PHY_TXD0" + (at 152.4 129.54 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "cf52562b-2c68-527a-a030-109668bb52f1") + ) + (label "PHY_TXD1" + (at 152.4 132.08 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "d245a0d1-7d48-58e2-aaf1-eba4a95da8a7") + ) + (label "PHY_TXD2" + (at 152.4 134.62 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "8ae67af4-9d57-5011-bbe2-6484b751d946") + ) + (label "PHY_TXD3" + (at 152.4 137.16 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "7e4ae8b2-4ec5-5067-97d4-1649ca38cecf") + ) + (label "PHY_RXC" + (at 152.4 139.7 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "2e0f599f-30b5-5467-afda-83003a9749f5") + ) + (label "PHY_RXCTL" + (at 152.4 142.24 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "866f11e0-772f-507a-abf6-e108e4085ddc") + ) + (label "PHY_RXD0" + (at 152.4 144.78 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "950ffb86-43de-5c04-94bc-ecdd5c056a75") + ) + (label "PHY_RXD1" + (at 152.4 147.32 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "4f13a1f9-fd5b-5b89-b7ac-cd056badc8cc") + ) + (label "PHY_RXD2" + (at 152.4 149.86 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "7ecb2c50-858f-5fe5-8907-0fea8a86f735") + ) + (label "PHY_RXD3" + (at 152.4 152.4 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "4f893596-1f08-538f-80bf-6246bc803275") + ) + (global_label "ENET_MDC" + (shape input) + (at 152.4 154.94 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "8f7b6032-b93a-5676-a069-5132847a90c1") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 152.4 154.94 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "ENET_MDIO" + (shape bidirectional) + (at 152.4 157.48 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "17a6edc7-9679-5b49-b14e-c3350b94d860") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 152.4 157.48 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "ENET_INT_N" + (shape output) + (at 152.4 160.02 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "8704a891-e7eb-568a-a8c1-c5f61e992932") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 152.4 160.02 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "ENET_RST_N" + (shape input) + (at 152.4 162.56 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "a1e1c9bd-0db6-5243-8d56-d2cafc984443") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 152.4 162.56 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "MDI0_P" + (at 228.6 127 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "e6528cd2-a5bd-5e19-a659-d1b1be64e2f1") + ) + (label "MDI0_N" + (at 228.6 129.54 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "b827b1b0-a680-5905-8073-92ceae093797") + ) + (label "MDI1_P" + (at 228.6 132.08 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "069e9f00-14e1-5995-81f5-c4373fb54597") + ) + (label "MDI1_N" + (at 228.6 134.62 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "24567d50-5088-5352-8aae-69ada4da0177") + ) + (label "MDI2_P" + (at 228.6 137.16 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "0cea8be1-0ac9-5b01-ac68-9e0fd6e5eaec") + ) + (label "MDI2_N" + (at 228.6 139.7 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "4ab097bf-c767-5778-8352-1c86976070ef") + ) + (label "MDI3_P" + (at 228.6 142.24 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "25359506-5253-5e7d-84c4-2349f5f76e01") + ) + (label "MDI3_N" + (at 228.6 144.78 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "fbe75b27-967b-5887-82a7-869ca333df88") + ) + (label "PHY_LED0" + (at 228.6 147.32 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "3237c03a-ce6c-5ec1-9feb-4b4248757d80") + ) + (label "PHY_LED1" + (at 228.6 149.86 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "b3a21423-a7db-5fc4-a86c-e27ddd2a2842") + ) + (label "PHY_LED2" + (at 228.6 152.4 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "a095c987-e841-58f4-9770-2d59feb3294c") + ) + (label "PHY_XTAL_IN" + (at 228.6 154.94 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "7dbcf09d-aa7b-5659-9042-e5f296161451") + ) + (label "PHY_XTAL_OUT" + (at 228.6 157.48 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "c7f9897a-558b-5687-a2cc-243a88587769") + ) + (label "PHY_RSET" + (at 228.6 160.02 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "fe6614d9-8caf-5f13-bfa9-def76e730ed7") + ) + (label "PHY_REG_OUT" + (at 228.6 162.56 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "1da1382a-069a-59d9-837a-9bd130bc5070") + ) + (label "ETH_AVDD33" + (at 190.5 93.98 90) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "1fce8a58-2986-533a-bfad-a2b5ca4a9b5a") + ) + (label "ETH_1V0" + (at 205.74 101.6 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "255114e6-9f79-5bfb-8cd3-2a63a945315f") + ) + (global_label "ENET_GTX_CLK" + (shape input) + (at 57.15 55.88 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "b14e3100-30aa-5f5e-968f-cb8cc320c252") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 55.88 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "PHY_TXC" + (at 74.93 55.88 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "9db4b2e2-5edc-5cf4-8f57-1edf256625a8") + ) + (global_label "ENET_TX_EN" + (shape input) + (at 57.15 63.5 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "551d739b-06fb-56df-84f4-9eb83149a2e3") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 63.5 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "PHY_TXCTL" + (at 74.93 63.5 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "37fabea3-9e8d-5f57-a4d0-46cffc9c0c5c") + ) + (global_label "ENET_TX_DATA0" + (shape input) + (at 57.15 71.12 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "7ddf2b02-0cce-5251-9e9e-c386a3f6b016") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 71.12 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "PHY_TXD0" + (at 74.93 71.12 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "f25f9eea-2996-56e0-8460-387b737d6f18") + ) + (global_label "ENET_TX_DATA1" + (shape input) + (at 57.15 78.74 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2dce0093-c59f-5ec3-b9df-73a7326affaf") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 78.74 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "PHY_TXD1" + (at 74.93 78.74 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "ac46a5e4-6053-5325-bcca-a5591f14f2f9") + ) + (global_label "ENET_TX_DATA2" + (shape input) + (at 57.15 86.36 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "f0c835e9-1c78-52fe-adf6-c7fff06f43f2") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 86.36 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "PHY_TXD2" + (at 74.93 86.36 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "7a014fab-a48e-5013-815d-78b8bdf490ec") + ) + (global_label "ENET_TX_DATA3" + (shape input) + (at 57.15 93.98 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2c5d33dd-10b8-5059-bff5-27f827cc2ba3") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 93.98 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "PHY_TXD3" + (at 74.93 93.98 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "52fc9691-1913-5766-981d-c14f617ad2d9") + ) + (global_label "ENET_RX_CLK" + (shape output) + (at 57.15 106.68 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "ffb8bf4a-0a42-5988-ac31-e232bb3cbec6") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 57.15 106.68 180) + (effects + (font + (size 1.27 1.27) + ) + (justify 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"a860af7f-ac5a-55a8-9e55-072d76ef32e7") + ) + (pin "2" + (uuid "4c4ab1cb-02e8-561b-927e-9974d9d73473") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d2db0303-8307-5ff1-a177-f397fed4cfb9" + (reference "R51") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 391.16 160.02 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "b2d25238-36c5-5114-a48b-4dd6e46a0153") + (property "Reference" "#PWR141" + (at 391.16 166.37 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 389.255 164.465 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 391.16 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 391.16 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 391.16 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "af17a371-b44c-5dff-ad73-34d6ef5f53fd") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d2db0303-8307-5ff1-a177-f397fed4cfb9" + (reference "#PWR141") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 365.76 156.21 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "f913249a-0b9a-5834-87e7-fc5169d81c4a") + (property "Reference" "C64" + (at 368.3 154.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "100nF" + (at 368.3 157.48 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0402_1005Metric" + (at 365.76 156.21 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 365.76 156.21 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 365.76 156.21 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1525" + (at 365.76 156.21 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL05B104KO5NNNC" + (at 365.76 156.21 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Samsung Electro-Mechanics" + (at 365.76 156.21 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "4203bf70-64f6-56b5-9d15-d27fb240536d") + ) + (pin "2" + (uuid "86106a3f-0d2a-51f9-b0f3-d0a5d937c846") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d2db0303-8307-5ff1-a177-f397fed4cfb9" + (reference "C64") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 365.76 160.02 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "185f5e6a-1ff5-52a8-a04d-cfd71b7fa8f7") + (property "Reference" "#PWR142" + (at 365.76 166.37 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 363.855 164.465 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 365.76 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 365.76 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 365.76 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "15109835-eda0-5a65-b163-84cdee735136") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d2db0303-8307-5ff1-a177-f397fed4cfb9" + (reference "#PWR142") + (unit 1) + ) + ) + ) + ) + (embedded_fonts no) +) diff --git a/kicad/fp-lib-table b/kicad/fp-lib-table new file mode 100644 index 0000000..614c751 --- /dev/null +++ b/kicad/fp-lib-table @@ -0,0 +1,4 @@ +(fp_lib_table + (version 7) + (lib (name "eboard")(type "KiCad")(uri "${KIPRJMOD}/lib/eboard.pretty")(options "")(descr "eboard project footprints")) +) diff --git a/kicad/fpga_banks_01.kicad_sch b/kicad/fpga_banks_01.kicad_sch new file mode 100644 index 0000000..93c6494 --- /dev/null +++ b/kicad/fpga_banks_01.kicad_sch @@ -0,0 +1,4937 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "306a6304-f946-5685-a692-5627b40d751c") + (paper "A4") + (title_block + (title "eboard - FPGA banks 0 1") + (date "2026-11-08") + (rev "0.1") + (comment 1 "CERN-OHL-S-2.0") + ) + (lib_symbols +(symbol "eboard_fpga:LFE5U-25F-xBG256x" +(property "Reference" "U" + (at -36.83 33.02 0) + (effects + (font + (size 1.27 1.27)) + (justify right) + (hide no))) +(property "Value" "LFE5U-25F-xBG256x" + (at -36.83 30.480000000000004 0) + (effects + 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Pmod A/B.\nGPIO_0[0] / [2] on PCLKT1_0 C8 / PCLKT1_1 E8; GPIO_0[2k] / [2k+1]\non the true / complement ball of a pair (header neighbours)." + (exclude_from_sim no) + (at 182.88 134.62 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "bb752999-6617-5e9e-8056-317981288cae") + ) + (text "FPGA banks 0 and 1" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "6cc17d4f-63c0-5196-b591-c29f8530a055") + ) + (text "All banks VCCIO = 3.3 V. Ball assignment preliminary (PINPLAN.md): pins may be\nswapped within a bank during layout; the LPF follows the schematic.\nBalls B1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs on the 45F) carry no clocks." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "a6759d21-a811-5326-8b23-6dc86814716f") + ) + (global_label "ENET_RX_DV" + (shape input) + (at 45.72 86.36 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "cfa7283e-9f66-58a6-8489-189b21b0da0b") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 86.36 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "ENET_RX_DATA0" + (shape input) + (at 45.72 88.9 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "f375f5fa-85ab-56eb-aa9d-18a5786f0ed5") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 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246.38 86.36) + ) + (stroke + (width 0) + (type default) + ) + (uuid "e0056dd2-d5f5-5443-96ad-de5eb77352bc") + ) + (wire + (pts + (xy 243.84 88.9) (xy 246.38 88.9) + ) + (stroke + (width 0) + (type default) + ) + (uuid "a285ff68-24b9-5fb7-8a8c-cdb2d4e1fbbc") + ) + (wire + (pts + (xy 243.84 91.44) (xy 246.38 91.44) + ) + (stroke + (width 0) + (type default) + ) + (uuid "8ae9f46b-4877-5a55-971a-08a19001d107") + ) + (wire + (pts + (xy 243.84 93.98) (xy 246.38 93.98) + ) + (stroke + (width 0) + (type default) + ) + (uuid "a7205df3-c774-555b-8ba8-b7b7f72e13d8") + ) + (wire + (pts + (xy 243.84 96.52) (xy 246.38 96.52) + ) + (stroke + (width 0) + (type default) + ) + (uuid "cca5e401-6978-5a1a-8bcf-1876911d5b45") + ) + (wire + (pts + (xy 243.84 99.06) (xy 246.38 99.06) + ) + (stroke + (width 0) + (type default) + ) + (uuid "739810ce-05f3-57d6-a6e6-b6595284b664") + ) + (wire + (pts + (xy 243.84 101.6) (xy 246.38 101.6) + ) + (stroke + (width 0) + (type default) + ) + (uuid "a4140da0-2f49-5c7b-b83f-c8ac18a63ed2") + ) + (wire + (pts + (xy 243.84 104.14) (xy 246.38 104.14) + ) + (stroke + (width 0) + (type default) + ) + (uuid "ff6ca172-2c3a-5dbe-87ac-2676bb8ee10e") + ) + (wire + (pts + (xy 243.84 106.68) (xy 246.38 106.68) + ) + (stroke + (width 0) + (type default) + ) + (uuid "1e8f08ab-e071-5579-af50-6f95b03aa914") + ) + (wire + (pts + (xy 243.84 109.22) (xy 246.38 109.22) + ) + (stroke + (width 0) + (type default) + ) + (uuid "53ffbd3c-6213-521d-a01f-b8f7b791d8dd") + ) + (wire + (pts + (xy 243.84 111.76) (xy 246.38 111.76) + ) + (stroke + (width 0) + (type default) + ) + (uuid "ba3c19f4-d7e3-550e-ad75-1d99281a7c90") + ) + (wire + (pts + (xy 243.84 114.3) (xy 246.38 114.3) + ) + (stroke + (width 0) + (type default) + ) + (uuid "4eb260bf-3dea-54be-b782-12dfca270391") + ) + (wire + (pts + (xy 243.84 116.84) (xy 246.38 116.84) + ) + (stroke + (width 0) + (type default) + ) + (uuid "f5546684-c881-5a5d-a2f1-f96491e954c4") + ) + (wire + (pts + (xy 243.84 119.38) (xy 246.38 119.38) + ) + (stroke + (width 0) + (type default) + ) + (uuid "4a4faf65-cf95-5a4b-a932-82f524d0b518") + ) + (text "Bank 2 (right upper): GPIO_1[31:0].\nGPIO_1[0] / [2] on PCLKT2_0 K16 / PCLKT2_1 J16; GPIO_1[2k] / [2k+1]\non true LVDS pairs (A/B, C/D)." + (exclude_from_sim no) + (at 48.26 134.62 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "85975bf4-f8ba-5a4b-a5d1-721e67a99bf7") + ) + (text "Bank 3 (right lower): GPIO_1[35:32] (pairs PR26),\nUART_TXD / UART_RXD, HEX0-HEX2, HEX3[4:0]." + (exclude_from_sim no) + (at 182.88 134.62 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "c7212ed0-71c8-5107-b6d2-cf1b8caab32c") + ) + (text "FPGA banks 2 and 3" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "167ff5b5-a5f5-5490-a08d-6a0a83d65b64") + ) + (text "All banks VCCIO = 3.3 V. Ball assignment preliminary (PINPLAN.md): pins may be\nswapped within a bank during layout; the LPF follows the schematic.\nBalls B1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs on the 45F) carry no clocks." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "06089e3d-6fba-532e-bdca-cf6b94308291") + ) + (global_label "GPIO_1_1" + (shape bidirectional) + (at 45.72 81.28 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "45116652-2979-5c77-ba9d-eb0c4c169070") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 81.28 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_3" + (shape bidirectional) + (at 45.72 83.82 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d19881ef-0d73-5cc8-bc76-c67470d76460") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 83.82 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_0" + (shape bidirectional) + (at 45.72 86.36 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "84753311-da3a-5a40-98f5-7b2f3c984863") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 86.36 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_2" + (shape bidirectional) + (at 45.72 88.9 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "0df6f82f-13f6-5b2d-9016-7e3e5e2ba490") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 88.9 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_5" + (shape bidirectional) + (at 45.72 91.44 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d73ee75e-c0dc-5dbb-8236-0bbee38e9588") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 91.44 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_7" + (shape bidirectional) + (at 45.72 93.98 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "54306b17-064b-573a-9317-7e12b50f0b6a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 93.98 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_4" + (shape bidirectional) + (at 45.72 96.52 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "be55407d-19a0-5935-9c8e-c1afe85b0c05") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 96.52 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_6" + (shape bidirectional) + (at 45.72 99.06 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "379dde0f-1a31-5ee5-9707-a21c093997ce") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 99.06 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_9" + (shape bidirectional) + (at 45.72 101.6 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "e77f3773-61d6-53c0-b1b6-05a7bd18befb") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 101.6 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_11" + (shape bidirectional) + (at 45.72 104.14 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "77706a4b-b7d4-5595-90af-c8afc693ce36") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 104.14 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_8" + (shape bidirectional) + (at 45.72 106.68 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "227bac22-a01d-5c82-af01-082fc8cc28af") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 106.68 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_10" + (shape bidirectional) + (at 45.72 109.22 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "08920cce-454b-554d-ad36-842c97d6a0ad") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 109.22 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_13" + (shape bidirectional) + (at 45.72 111.76 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "7aa15457-78af-53d3-9904-60a75009cc60") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 111.76 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_15" + (shape bidirectional) + (at 45.72 114.3 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "68c2ebeb-b37e-5d0b-8929-f0941e47a5db") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 114.3 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_12" + (shape bidirectional) + (at 45.72 116.84 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "6f67bd08-ed79-5889-8a95-5520d7b83327") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 116.84 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_14" + (shape bidirectional) + (at 45.72 119.38 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "32f3e3db-342e-565d-8693-4fb7958ffae3") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 119.38 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_17" + (shape bidirectional) + (at 111.76 81.28 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "34e1eb8f-fa02-54f1-be40-c43d27b03968") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 81.28 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_19" + (shape bidirectional) + (at 111.76 83.82 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "2c00f769-e7d4-5b46-a7b6-24f1947736c5") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 83.82 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_16" + (shape bidirectional) + (at 111.76 86.36 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "08437df0-4f08-5440-9dde-a5f009ca3db5") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 86.36 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_18" + (shape bidirectional) + (at 111.76 88.9 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "229f18fd-89ee-5a3b-a5a8-831b63a5835b") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_21" + (shape bidirectional) + (at 111.76 91.44 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "9102e465-a29d-57b0-9b8d-0720dfb170d7") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 91.44 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_23" + (shape bidirectional) + (at 111.76 93.98 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "7a2709c7-717d-56ce-a5b2-c14bed65aa31") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 93.98 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_20" + (shape bidirectional) + (at 111.76 96.52 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "64794d0c-23f5-55d9-ad8c-e67bfc7983d2") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 96.52 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_22" + (shape bidirectional) + (at 111.76 99.06 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "2007946b-c4ce-540f-bde3-7a98e95470a3") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 99.06 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_25" + (shape bidirectional) + (at 111.76 101.6 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "09e3c904-b376-5989-8cef-698a973cbf2a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_27" + (shape bidirectional) + (at 111.76 104.14 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "1589c2e3-558e-5d20-b7a9-0d7503054b66") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_24" + (shape bidirectional) + (at 111.76 106.68 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "f5130d6c-ca77-5241-9afa-c06efaf79a8d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 106.68 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_26" + (shape bidirectional) + (at 111.76 109.22 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "4f9fcc74-d19f-5408-8a33-d9983d3a9caf") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 111.76 109.22 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_29" + (shape bidirectional) + (at 111.76 111.76 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "0c3b3960-a88d-57d2-afeb-c4dba2bb79e3") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + 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Ball assignment preliminary (PINPLAN.md): pins may be\nswapped within a bank during layout; the LPF follows the schematic.\nBalls B1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs on the 45F) carry no clocks." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ab6d93d6-2965-5c39-859b-af79ad267be4") + ) + (global_label "DRAM_CAS_N" + (shape output) + (at 45.72 81.28 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "974bfe93-a5ab-532d-bd58-d490d28854e4") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 81.28 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "CLOCK_50" + (shape input) + (at 45.72 83.82 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d6f92d7e-d893-5ea8-8f30-60baa2973ff9") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 45.72 83.82 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236.22 45.72) + ) + (stroke + (width 0) + (type default) + ) + (uuid "8fc650c9-35e8-52ac-87f7-d725c9268154") + ) + (text "Pull-ups to VCCIO8 (TN-02038 Table 6.2).\nFLASH_CS and FLASH_CLK pull-ups next to the flash." + (exclude_from_sim no) + (at 129.54 55.88 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "d4d26640-648a-5362-9bb9-a60db1f4792d") + ) + (text "MCLK series R close to the FPGA ball N9" + (exclude_from_sim no) + (at 147.32 35.56 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "33746bfa-d981-57f7-abdc-5edb9f536b37") + ) + (text "Bank 8 (VCCIO8 = 3.3 V): SPI flash; the other bank 8 I/O drive LEDG[5:0]\nand HEX3[6:5] (they may toggle during configuration)." + (exclude_from_sim no) + (at 45.72 139.7 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "0a8e2aba-0678-571c-a6b2-13d0fe31addf") + ) + (text "PROG button" + (exclude_from_sim no) + (at 45.72 163.83 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "f1ab4dfc-a84d-5685-9c24-116091d6749f") + ) + (text "DONE LED" + (exclude_from_sim no) + (at 63.5 154.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "61638a51-1c10-5526-aaec-cf1a9e287d54") + ) + (text "50 MHz system clock (as on the DE1). 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(wire + (pts + (xy 114.3 130.81) (xy 127 130.81) + ) + (stroke + (width 0) + (type default) + ) + (uuid "b3c00791-34f1-52cd-bc9f-001382e1268d") + ) + (wire + (pts + (xy 127 130.81) (xy 139.7 130.81) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fc3d1f6d-6fae-553d-9f68-d22028427de8") + ) + (wire + (pts + (xy 139.7 130.81) (xy 152.4 130.81) + ) + (stroke + (width 0) + (type default) + ) + (uuid "621dbc3d-5c2d-544e-829d-22574d6b9bce") + ) + (wire + (pts + (xy 152.4 130.81) (xy 165.1 130.81) + ) + (stroke + (width 0) + (type default) + ) + (uuid "7cf3f704-9fe8-59c1-a3ec-187d34212ff3") + ) + (wire + (pts + (xy 165.1 130.81) (xy 177.8 130.81) + ) + (stroke + (width 0) + (type default) + ) + (uuid "1a0b4952-f73d-5bba-9bdd-f3016a5840dc") + ) + (wire + (pts + (xy 25.4 163.83) (xy 38.1 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "ac033a09-f1c5-5993-9ed2-76e0dc2cf5f9") + ) + (wire + (pts + (xy 38.1 163.83) (xy 50.8 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "3c801098-f117-580c-b36e-3efa0befe5fa") + ) + (wire + (pts + (xy 50.8 163.83) (xy 63.5 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fb96e8da-4f75-5d32-ba2c-733a1cc06219") + ) + (wire + (pts + (xy 63.5 163.83) (xy 76.2 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "eb5d013f-f34f-58d8-a01e-a39cb352ac34") + ) + (wire + (pts + (xy 76.2 163.83) (xy 88.9 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fd1e78a5-bd9d-5fa6-a35a-7a67aacd9b45") + ) + (wire + (pts + (xy 88.9 163.83) (xy 101.6 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "b0ba4361-108d-58c7-9606-c8e3c98a0b53") + ) + (wire + (pts + (xy 101.6 163.83) (xy 114.3 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "5763aaa5-0fe3-59f7-b03d-fea0741b513d") + ) + (wire + (pts + (xy 114.3 163.83) (xy 127 163.83) + ) + (stroke + (width 0) + (type default) + ) + (uuid "76729b29-01d0-53c8-afb8-4c29a929ab0d") + ) + (text "VCC 1.1 V core: 3 x 10 uF + 100 nF per VCC ball (G6 G7 G9 L8 L9 L10)" + (exclude_from_sim no) + (at 33.02 54.61 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "b665523d-dd28-5d2e-8c96-1949a3bee457") + ) + (text "VCCAUX 2.5 V: ferrite + 10 uF\n+ 100 nF per VCCAUX ball (G11 L7)" + (exclude_from_sim no) + (at 162.56 64.77 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "bf322b47-794f-5187-bba0-e0f9d2742c1f") + ) + (text "Bank0\nF6 F7" + (exclude_from_sim no) + (at 36.83 121.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ac476a1b-7af3-5887-9ec0-873ad9d621e6") + ) + (text "Bank1\nF10 F11" + (exclude_from_sim no) + (at 74.93 121.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "0bacad0a-e9a4-51f6-a5a6-cbc617acfc6b") + ) + (text "Bank2\nH11 J11" + (exclude_from_sim no) + (at 113.03 121.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "b7b9e38d-56a4-55b3-995a-3031f47fdcc1") + ) + (text "Bank3\nK11 L11" + (exclude_from_sim no) + (at 151.13 121.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "5fe37228-2870-53f8-87fc-e748e01653c7") + ) + (text "Bank6\nJ6 J7" + (exclude_from_sim no) + (at 36.83 154.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "99d36da1-2835-564f-b4bb-4e7404a69b2c") + ) + (text "Bank7\nH6 H7" + (exclude_from_sim no) + (at 74.93 154.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "e60bbb87-2842-5287-8e23-a961f60703cc") + ) + (text "Bank8\nL6" + (exclude_from_sim no) + (at 113.03 154.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ac73b41d-068d-5fc2-95f7-7b61141fc6cd") + ) + (text "FPGA power" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "1e95167c-732d-50af-ae72-21c2d2fc328d") + ) + (text "Decoupling per Lattice FPGA-TN-02038 (ECP5 hardware checklist) Table 3.1.\nPlace the 100 nF capacitors next to their balls, on the bottom side under the BGA.\nVCCIO: 10 uF + 100 nF per ball for every bank; all banks run at 3.3 V\n(VCCIO8 = 3.3 V also sets the JTAG and configuration levels).\nPOR needs VCC >= 0.9 V, VCCAUX >= 2.0 V, VCCIO8 >= 0.95 V." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "bf4b9996-8b38-5227-b36f-91b2825e5683") + ) + (text "U6: LFE5U-25F-7BG256I (24K LUTs, JLCPCB C1550762).\nDrop-in: LFE5U-45F-xBG256x (44K LUTs), same balls, banks and differential pairs;\nswap with 'Change symbol'. The 45F has 2 extra PLLs (upper corners): their inputs\nB1 B2 A2 B3 B14 A15 B15 B16 are plain I/O on the 25F -> no clocks on these balls." + (exclude_from_sim no) + (at 152.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "448410de-bd3a-55ce-8b6e-8912835b0ec2") + ) + (text "VCCIO decoupling (+3V3), 10 uF + 100 nF per ball" + (exclude_from_sim no) + (at 25.4 114.3 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "4af4bc69-89ba-540c-8b58-d90fc1d27b75") + ) + (label "FPGA_VCCAUX" + (at 152.4 76.2 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "6ff948fc-b78c-5368-ac4d-2850f4b0601b") + ) + (symbol + (lib_id "eboard_fpga:LFE5U-25F-xBG256x") + (at 147.32 104.14 0) + (unit 9) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "9cfd259a-46ba-5c7d-a594-a94b7f5152fa") + (property "Reference" "U6" + (at 152.4 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "LFE5U-25F-7BG256I" + (at 152.4 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Package_BGA:BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_Ball0.45mm_Pad0.32mm_NSMD" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "https://www.latticesemi.com/view_document?document_id=50461" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "ECP5 FPGA, 24K LUTs, 1.1V core, CABGA256" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1550762" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "LFE5U-25F-7BG256I" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Lattice" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Source" "Lattice pinout CSV FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv, package CABGA256" + (at 147.32 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "A1" + (uuid "ef6cb460-82a0-5ccc-90f6-4f47457acbca") + ) + (pin "A16" + (uuid "28ab053b-aabe-5a36-953c-8cec6ac5a416") + ) + (pin "D15" + (uuid "81506371-d104-5778-83d4-a2406a77965c") + ) + (pin "D2" + (uuid "2c5af4e9-8705-5c12-89c5-a8b550f7a3e0") + ) + (pin "F8" + (uuid "218f9735-b8ab-5619-82ab-72a4c2d46602") + ) + (pin "F9" + (uuid "93b9442c-483d-5015-aa7e-2cbe4836fbd4") + ) + (pin "G10" + (uuid "5dfc0adb-257d-5781-9e89-0a1b8a7df59b") + ) + (pin "G11" + (uuid "3f01d573-4a70-58de-a0b1-74e576e3faca") + ) + (pin "G6" + (uuid "977691a8-b85d-58e4-9928-22d43cd01473") + ) + (pin "G7" + (uuid "8e3f25b6-dbef-5ec6-8ec6-241d1b133c31") + ) + (pin "G8" + (uuid "3fe3fdbd-72fd-5b7f-96f2-5269aa0f6147") + ) + (pin "G9" + (uuid "a215b34a-333d-521e-aa61-93370dd5b751") + ) + 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104.14 236.22) + ) + (stroke + (width 0) + (type default) + ) + (uuid "2f75a33d-7b62-5a2a-b8ff-b2b246b6495c") + ) + (wire + (pts + (xy 134.62 231.14) (xy 139.7 231.14) + ) + (stroke + (width 0) + (type default) + ) + (uuid "89573893-36ab-53be-9e6c-24beb4d58c3f") + ) + (wire + (pts + (xy 134.62 236.22) (xy 139.7 236.22) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fe67de3e-76a1-5b23-a4f2-4c8418a8a7fc") + ) + (wire + (pts + (xy 355.6 114.3) (xy 355.6 116.84) + ) + (stroke + (width 0) + (type default) + ) + (uuid "19ef17ea-7953-533f-bce1-ef17747d03a3") + ) + (wire + (pts + (xy 381 114.3) (xy 381 116.84) + ) + (stroke + (width 0) + (type default) + ) + (uuid "a205116d-2cf3-5d20-bd9e-81c576290b84") + ) + (text "pin 37 POWER_ON = 1" + (exclude_from_sim no) + (at 341.63 96.52 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "7d1ad137-2215-587d-80f0-9f19eb14873a") + ) + (text "pin 38 ADC_OEB = 0" + (exclude_from_sim no) + (at 361.95 99.06 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "e33cc02a-e377-5223-9868-b8760c64c2a1") + ) + (text "pin 40 ADC_OEA = 0" + (exclude_from_sim no) + (at 382.27 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "bf371d74-c026-5838-b3de-612b9f53655a") + ) + (text "THDB-ADA: GPIO_0 pins 37-40 are not FPGA pins.\nPOWER_ON pull-up (ADC and clock buffer on),\nOEA/OEB pull-down (ADC outputs enabled), pin 39 unused." + (exclude_from_sim no) + (at 340.36 43.18 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "d3d3e9af-a250-55d8-80fa-22a77cbd2108") + ) + (text "Pmod A = GPIO_0_0..7, Pmod B = GPIO_0_8..15 (shared with GPIO_0:\nuse either a Pmod or a card on GPIO_0). Pmod pin 1-4 / 7-10 = IO 1-8.\nCheck pin 1 orientation against the Digilent Pmod specification in layout." + (exclude_from_sim no) + (at 248.92 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "e3bb7e33-9542-50b7-a0d0-f52a267bcdd5") + ) + (text "GPIO expansion headers (DE1 compatible), Pmod A/B, ESD protection" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "41021ecd-4820-5034-9729-18c0c9934a4e") + ) + (text "2x20 box headers at the DE1 positions (JP1 pin 1 at (125.603, 118.745) mm, JP2 20.32 mm to the right,\nsee PINPLAN.md). DE1 pinout: pins 1-10 = GPIO_x[0..9], 13-28 = [10..25], 31-40 = [26..35],\n12/30 = GND. Pin 29 = 3.3 V; pin 11 = 3.3 V instead of 5 V on the DE1: no 5 V on the headers.\nFPGA pins connected directly (as on ULX3S), ESD arrays close to the header pins." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "65808989-add5-5196-a52b-0852bf931c4b") + ) + (text "Scope ground loops (Keystone 5011, black) for the\ncrocodile clips: one at the GPIO headers, one at the Pmods." + (exclude_from_sim no) + (at 345.44 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "54d0fe8b-6276-5f65-908d-ec44db0a1976") + ) + (text "ESD protection TPD4E05U06 (DFN 2.5x1 mm, flow-through), one per 4 lines, placed at the headers" + (exclude_from_sim no) + (at 25.4 119.38 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "6488a233-9f5d-5db3-94d9-ba3a7ee39280") + ) + (global_label "GPIO_0_0" + (shape bidirectional) + (at 63.5 58.42 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "0b2d5dd7-2dba-50ce-9cfc-017ec59f08f3") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 58.42 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_1" + (shape bidirectional) + (at 91.44 58.42 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "74fd92dc-00b8-52ff-9fe9-6414ba5e6645") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 58.42 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_2" + (shape bidirectional) + (at 63.5 60.96 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "4204d506-7621-5d26-ab05-528fb53e8893") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 60.96 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_3" + (shape bidirectional) + (at 91.44 60.96 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "0dd37c4e-acc8-5732-93c4-4779c0145880") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 60.96 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_4" + (shape bidirectional) + (at 63.5 63.5 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "3217d1d3-6954-5d1b-b264-8091d1dcc8fa") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 63.5 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_5" + (shape bidirectional) + (at 91.44 63.5 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "af69ae44-7760-5d35-a189-553f1348e518") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_6" + (shape bidirectional) + (at 63.5 66.04 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "9e3d9772-814e-5013-8bf7-f4d2ea9af182") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 66.04 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_7" + (shape bidirectional) + (at 91.44 66.04 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "fe425aac-f3d5-5dae-88b0-fce37f8b53b4") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 66.04 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_8" + (shape bidirectional) + (at 63.5 68.58 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "ed4b0487-d5d1-58a5-86a4-525c130ce3da") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 68.58 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_9" + (shape bidirectional) + (at 91.44 68.58 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "ba24de97-d2ec-5576-b2b2-76c2afca6333") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 68.58 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_10" + (shape bidirectional) + (at 63.5 73.66 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "17d94e96-70ce-55e4-a1ea-9fd417ec4ed2") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 73.66 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_11" + (shape bidirectional) + (at 91.44 73.66 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "422680f9-071a-5b87-a0a6-c6bb6c06d771") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_12" + (shape bidirectional) + (at 63.5 76.2 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "c40c31ba-d13d-5b1f-bea4-0fae20b1cdb9") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 76.2 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_13" + (shape bidirectional) + (at 91.44 76.2 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "5cc9c17d-34ba-5673-b3e7-232e0be3d5e1") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 76.2 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_14" + (shape bidirectional) + (at 63.5 78.74 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "844488e6-7aa2-553e-9040-6e55e1c42244") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 78.74 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_15" + (shape bidirectional) + (at 91.44 78.74 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "fc999965-456b-5949-b25b-a8af7315ae0d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 78.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_16" + (shape bidirectional) + (at 63.5 81.28 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "c6ace35b-3d19-56c3-a569-44dcc05a5d1a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 81.28 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_17" + (shape bidirectional) + (at 91.44 81.28 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "5aa13ca5-d89f-5d77-974f-da07c1d30224") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 81.28 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_18" + (shape bidirectional) + (at 63.5 83.82 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "c30cb28d-a15d-5f2f-9765-acb568c83f30") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 83.82 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_19" + (shape bidirectional) + (at 91.44 83.82 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "53c735e7-0e98-52da-be95-2c54c4714df4") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 83.82 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_20" + (shape bidirectional) + (at 63.5 86.36 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "16bf283e-77f2-59b1-b331-ca073c761d33") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 86.36 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_21" + (shape bidirectional) + (at 91.44 86.36 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "56ae5fb0-d85a-5f11-aad2-e07aa9b87011") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 86.36 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_22" + (shape bidirectional) + (at 63.5 88.9 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "710d59a8-4911-51f3-a9ff-a34bf319e2ee") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 88.9 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_23" + (shape bidirectional) + (at 91.44 88.9 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "7f772405-7f79-503f-bd6e-f9893a34c7c8") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_24" + (shape bidirectional) + (at 63.5 91.44 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "80cae3c9-abe0-55a0-a48c-aeaacfaeca20") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 91.44 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_25" + (shape bidirectional) + (at 91.44 91.44 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "47628a21-faa8-5762-8032-0b3b5fb19914") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 91.44 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_26" + (shape bidirectional) + (at 63.5 96.52 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "6eff652b-43b0-53b5-b7f7-31eea243a309") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 96.52 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_27" + (shape bidirectional) + (at 91.44 96.52 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid 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180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "9113727b-4a2a-5467-9960-b6a39f583ea6") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 63.5 101.6 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_0_31" + (shape bidirectional) + (at 91.44 101.6 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "861f672a-4584-57b2-bcd5-0b60fa946837") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 91.44 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (label "ADA_POWER_ON" + (at 45.72 104.14 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "76c4c896-5a30-5bf1-a8ba-b02939ee7237") + ) + (label "ADA_OEB" + (at 109.22 104.14 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) 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180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_5" + (shape bidirectional) + (at 205.74 63.5 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "b9fc59d2-192d-5dc3-9967-0f91551e107c") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 205.74 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_6" + (shape bidirectional) + (at 177.8 66.04 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "ea3945ac-be63-56c1-8bc4-28058b544379") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 177.8 66.04 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "GPIO_1_7" + (shape bidirectional) + (at 205.74 66.04 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid 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113.03 134.62) + ) + (stroke + (width 0) + (type default) + ) + (uuid "d5ebf57d-d296-5fa5-aad9-01d2e83cc984") + ) + (wire + (pts + (xy 83.82 152.4) (xy 78.74 152.4) + ) + (stroke + (width 0) + (type default) + ) + (uuid "4933093f-56a6-5406-b8b1-8a3989962dcf") + ) + (wire + (pts + (xy 83.82 157.48) (xy 78.74 157.48) + ) + (stroke + (width 0) + (type default) + ) + (uuid "305cf236-5ebe-5cab-8032-c7df993dfd76") + ) + (wire + (pts + (xy 109.22 152.4) (xy 114.3 152.4) + ) + (stroke + (width 0) + (type default) + ) + (uuid "97aa8bab-e4de-551e-8cf2-0667b5cb938b") + ) + (wire + (pts + (xy 109.22 157.48) (xy 114.3 157.48) + ) + (stroke + (width 0) + (type default) + ) + (uuid "b9306942-4eca-57af-a71c-1ce9acca9527") + ) + (wire + (pts + (xy 152.4 152.4) (xy 147.32 152.4) + ) + (stroke + (width 0) + (type default) + ) + (uuid "5ccc5266-fc78-573e-bbea-2d8fdfa4fee5") + ) + (wire + (pts + (xy 152.4 157.48) (xy 147.32 157.48) + ) + (stroke + (width 0) + (type default) + ) + (uuid "edcb517c-9b0c-5165-aea4-d5636cbd59ff") + ) + (wire + (pts + (xy 177.8 152.4) (xy 182.88 152.4) + ) + (stroke + (width 0) + (type default) + ) + (uuid "d5be8a56-afd4-5882-b51c-a0d953667af6") + ) + (wire + (pts + (xy 177.8 157.48) (xy 182.88 157.48) + ) + (stroke + (width 0) + (type default) + ) + (uuid "24540d33-0a62-5a6c-99de-d517b846ffe4") + ) + (text "ESD protection TPD4E05U06 (0.3 pF), at the connector,\nbetween connector and coupling capacitors" + (exclude_from_sim no) + (at 25.4 172.72 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "668aa40b-ab24-5959-9a68-b281bbdadffb") + ) + (text "HDMI output (type A), TMDS driven directly by the FPGA" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "fa2ad14a-bb29-582e-926b-00fb5b247746") + ) + (text "FPGA bank 0, each pair on an A/B ball pair, IO_TYPE=LVCMOS33D (as ULX3S GPDI). 640x480 and 720p work\nwith the ECP5 serializers (ODDRX1F/ODDRX2F). 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"RJ45_Hanrun_HR911130A_Horizontal_1_0" + (text "75" + (at -1.524 8.382 0) + (effects + (font + (size 0.508 0.508) + ) + ) + ) + (text "75" + (at -1.524 0.762 0) + (effects + (font + (size 0.508 0.508) + ) + ) + ) + (text "75" + (at -1.524 -6.858 0) + (effects + (font + (size 0.508 0.508) + ) + ) + ) + (text "75" + (at -1.524 -14.478 0) + (effects + (font + (size 0.508 0.508) + ) + ) + ) + ) + (symbol "RJ45_Hanrun_HR911130A_Horizontal_1_1" + (text "1000pF 2kV" + (at -3.81 -16.256 0) + (effects + (font + (size 0.635 0.635) + ) + (justify left) + ) + ) + (text "Y" + (at 2.54 15.24 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin passive line + (at 12.7 15.24 180) + (length 2.54) + (name "CT" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 12.7 12.7 180) + (length 2.54) + (name "MDI0+" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "2" + (effects + (font + (size 1.27 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(at 12.7 -10.16 180) + (length 2.54) + (name "MDI3+" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "8" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 12.7 -15.24 180) + (length 2.54) + (name "MDI3-" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "9" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at -5.08 20.32 270) + (length 2.54) + (name "LGA" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "11" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at -2.54 20.32 270) + (length 2.54) + (name "LGK" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "12" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 5.08 20.32 270) + (length 2.54) + (name "LYK" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "13" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 2.54 20.32 270) + (length 2.54) + (name "LYA" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "14" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 5.08 -20.32 90) + (length 2.54) + (name "SH" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "SH" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + (embedded_fonts no) + ) +) diff --git a/kicad/lib/tools/ch347f.csv b/kicad/lib/tools/ch347f.csv new file mode 100644 index 0000000..ad27b48 --- /dev/null +++ b/kicad/lib/tools/ch347f.csv @@ -0,0 +1,37 @@ +CH347F +Footprint:,Package_DFN_QFN:QFN-28-1EP_4x4mm_P0.4mm_EP2.4x2.4mm_ThermalVias +Datasheet:,https://www.wch-ic.com/downloads/CH347DS1_PDF.html +Description:,"High-speed USB 2.0 to dual UART, I2C, SPI, JTAG, SWD converter, VIO 1.8-3.3V, QFN-28 (datasheet pin 0 = EP = pad 29)" +Source*:,"WCH CH347 datasheet V1.4 (CH347DS1): CH347F pins tables 4-1 to 4-7, pin names from the pinout figure (page 4); EP = datasheet pin 0 = pad 29" +Keywords:,USB UART JTAG SPI I2C SWD converter WCH +Filters:,QFN*28*1EP*4x4mm*P0.4mm* +pin,name,type,side +21,VCC,power_in,top +6,VIO,power_in,top +3,~{RST},input,left +1,XI,input,left +2,XO,output,left +28,UD+,bidirectional,left +27,UD-,bidirectional,left +8,ACT/SRST,output,left +20,GND,power_in,bottom +29,GND,passive,bottom +19,TXD0,output,right +22,RXD0,input,right +18,RTS0/GPIO1,bidirectional,right +17,CTS0/GPIO0,bidirectional,right +10,DTR0/TNOW0/GPIO2,bidirectional,right +4,TXD1,output,right +5,RXD1,input,right +11,CTS1/SCL,bidirectional,right +12,RTS1/SDA,bidirectional,right +7,DTR1/TNOW1/SCS1,bidirectional,right +14,SCK,output,right +13,SCS0,output,right +16,MOSI,output,right +15,MISO,input,right +23,TCK/SWDCLK/GPIO4,output,right +26,TMS/SWDIO/GPIO7,bidirectional,right +25,TDI/GPIO6,output,right +24,TDO/GPIO5,input,right +9,TRST/GPIO3,bidirectional,right diff --git a/kicad/lib/tools/derive_symbol.py b/kicad/lib/tools/derive_symbol.py new file mode 100755 index 0000000..1278128 --- /dev/null +++ b/kicad/lib/tools/derive_symbol.py @@ -0,0 +1,74 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-3.0-or-later +"""Add a pin-compatible variant of a symbol to a KiCad symbol library. + +The variant keeps the geometry of the base symbol (every pin number at the +same position), so "Change symbol" in the schematic swaps the two without +breaking wires. Pin names and the description come from the variant's kipart +CSV (as written by lattice2kipart.py). + + derive_symbol.py LIB.kicad_sym BASE_NAME VARIANT.csv > OUT.kicad_sym +""" +import csv +import re +import sys + + +def match_paren(t, i): + depth = 0 + j = i + while True: + c = t[j] + if c == '"': + j += 1 + while t[j] != '"': + j += 2 if t[j] == "\\" else 1 + elif c == "(": + depth += 1 + elif c == ")": + depth -= 1 + if depth == 0: + return j + 1 + j += 1 + + +lib_path, base, var_csv = sys.argv[1:4] +lib = open(lib_path).read() + +rows = list(csv.reader(open(var_csv, newline=""))) +variant = rows[0][0] +props = {r[0][:-1].replace("*", ""): r[1] for r in rows[1:] if r and r[0].endswith(":")} +hdr = next(i for i, r in enumerate(rows) if r and r[0] == "pin") +cols = rows[hdr] +pins = {r[cols.index("pin")]: (r[cols.index("name")], r[cols.index("type")]) + for r in rows[hdr + 1:] if r and r[0]} + +m = re.search(r'\(symbol "' + re.escape(base) + r'"', lib) +start = m.start() +block = lib[start:match_paren(lib, start)] +base_types = {n: t for t, n in re.findall(r'\(pin (\w+) \w+ .*?\(number "([^"]+)"', block, re.S)} + +new = block.replace(f'(symbol "{base}"', f'(symbol "{variant}"', 1) +new = new.replace(f'(symbol "{base}_', f'(symbol "{variant}_') +new = re.sub(r'(\(property "Value" )"[^"]*"', rf'\1"{variant}"', new, count=1) +for key in ("Description", "Source"): + if key in props: + new = re.sub(r'(\(property "' + key + r'" )"[^"]*"', lambda mm: f'{mm.group(1)}"{props[key]}"', + new, count=1) + + +def rename(mm): + num = mm.group(3) + name, typ = pins[num] + if typ != base_types[num] and not (base_types[num] == "passive"): # stacked pins are passive + sys.exit(f"pin {num}: type {typ} differs from {base_types[num]}") + return f'{mm.group(1)}(name "{name}"{mm.group(2)}(number "{num}"' + + +new, n = re.subn(r'(\(pin [^\n]*\n(?:(?!\(pin ).)*?)\(name "[^"]*"(.*?)\(number "([^"]+)"', + rename, new, flags=re.S) +if n != len(pins): + sys.exit(f"renamed {n} pins, variant has {len(pins)}") + +end = match_paren(lib, start) +sys.stdout.write(lib[:end] + "\n " + new + lib[end:]) diff --git a/kicad/lib/tools/kicad_sym_grid.py b/kicad/lib/tools/kicad_sym_grid.py new file mode 100755 index 0000000..de52a8e --- /dev/null +++ b/kicad/lib/tools/kicad_sym_grid.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-3.0-or-later +"""Snap kipart symbol pins onto the 2.54 mm grid. + +kipart centres each pin column, which puts columns with an even pin count +(and box edges) on a 1.27 mm half grid; it also writes float noise such as +3.55e-15. Pins are moved by half a grid step along their column, and pins +whose end point is off grid are lengthened so the symbol body stays put. + + kicad_sym_grid.py IN.kicad_sym > OUT.kicad_sym +""" +import re +import sys + + +def on_grid(v): + return abs(v / 2.54 - round(v / 2.54)) < 0.004 + + +def fix(m): + kind, x, y, a = m.group(1), float(m.group(2)), float(m.group(3)), m.group(4) + length = float(m.group(5)) + vertical = a in ("90", "270") + if vertical and not on_grid(x): + x += 1.27 + if not vertical and not on_grid(y): + y += 1.27 + if vertical and not on_grid(y): + y += 1.27 if y > 0 else -1.27 + length += 1.27 + if not vertical and not on_grid(x): + x += 1.27 if x > 0 else -1.27 + length += 1.27 + + def f(v): + v = round(v, 4) + return "0" if v == 0 else f"{v:g}" + return f"(pin {kind} (at {f(x)} {f(y)} {a}) (length {f(length)})" + + +text = open(sys.argv[1]).read() +text = re.sub(r"\(pin ([\w ]+?)\s*\(at ([-\d.e+]+) ([-\d.e+]+) (\d+)\)\s*\(length ([\d.]+)\)", + fix, text) +sys.stdout.write(text) diff --git a/kicad/lib/tools/lattice2kipart.py b/kicad/lib/tools/lattice2kipart.py new file mode 100755 index 0000000..3e10074 --- /dev/null +++ b/kicad/lib/tools/lattice2kipart.py @@ -0,0 +1,107 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-3.0-or-later +"""Convert a Lattice ECP5 pinout CSV into a kipart input CSV. + +Usage: + lattice2kipart.py PINOUT.csv PACKAGE PARTNAME FOOTPRINT LUTS > part.csv + kipart -b -o out.kicad_sym part.csv + +One unit per I/O bank, one unit for configuration/JTAG, one unit for +core/aux power and ground. Dual functions are appended to the pin name +(e.g. PL32A/PCLKT7_1) so clock and config pins are visible in the schematic. +""" +import csv +import os +import re +import sys + +IO_RE = re.compile(r"P[TBLR]\d+[A-D]$") + +# Dedicated pins: name -> (kicad name, type, side, unit) +DEDICATED = { + "PROGRAMN": ("~{PROGRAMN}", "input", "left", "Config"), + "INITN": ("~{INITN}", "open_collector", "left", "Config"), + "DONE": ("DONE", "open_collector", "left", "Config"), + "CCLK": ("CCLK", "bidirectional", "left", "Config"), + "CFG_0": ("CFG_0", "input", "left", "Config"), + "CFG_1": ("CFG_1", "input", "left", "Config"), + "CFG_2": ("CFG_2", "input", "left", "Config"), + "TCK": ("TCK", "input", "right", "Config"), + "TMS": ("TMS", "input", "right", "Config"), + "TDI": ("TDI", "input", "right", "Config"), + "TDO": ("TDO", "output", "right", "Config"), + "VCC": ("VCC", "power_in", "top", "Power"), + "VCCAUX": ("VCCAUX", "power_in", "top", "Power"), + "GND": ("GND", "power_in", "bottom", "Power"), +} + + +def main(): + src, package, part, footprint, luts = sys.argv[1:6] + rows = [r for r in csv.reader(open(src, newline="")) + if r and any(c.strip() for c in r) and not r[0].startswith("#")] + header = rows[0] + pins = [dict(zip(header, r)) for r in rows[1:]] + if package not in header: + sys.exit(f"package {package} not in {header}") + pins = [p for p in pins if p[package].strip() not in ("", "-")] + + # Split each bank's IOs: first half left side, second half right side. + banks = {} + for p in pins: + if IO_RE.match(p["Pin/Ball Function"]): + banks.setdefault(p["Bank"], []).append(p) + side_of = {} + for b, lst in banks.items(): + half = (len(lst) + 1) // 2 + for i, p in enumerate(lst): + side_of[id(p)] = "left" if i < half else "right" + + out = csv.writer(sys.stdout) + out.writerow([part]) + out.writerow(["Footprint:", footprint]) + out.writerow(["Datasheet:", + "https://www.latticesemi.com/view_document?document_id=50461"]) + out.writerow(["Description:", + f"ECP5 FPGA, {luts} LUTs, 1.1V core, {package}"]) + out.writerow(["Source*:", f"Lattice pinout CSV {os.path.basename(src)}, package {package}"]) + out.writerow(["Keywords:", "FPGA programmable logic Lattice ECP5"]) + out.writerow(["Filters:", "BGA*256*14.0x14.0mm*P0.8mm*"]) + out.writerow(["pin", "name", "type", "side", "unit"]) + + rows_out = [] + seen = set() + for p in pins: + ball = p[package].strip() + if ball in seen: + sys.exit(f"duplicate ball {ball}") + seen.add(ball) + func = p["Pin/Ball Function"].strip() + dual = p["Dual Function"].strip() + bank = p["Bank"].strip() + if IO_RE.match(func): + name = func if dual in ("", "-") else f"{func}/{dual}" + rows_out.append([ball, name, "bidirectional", side_of[id(p)], + f"Bank{bank}"]) + elif func.startswith("VCCIO"): + rows_out.append([ball, func, "power_in", "top", f"Bank{bank}"]) + elif func in DEDICATED: + name, typ, side, unit = DEDICATED[func] + if func == "CCLK" and dual not in ("", "-"): + name = f"CCLK/{dual}" + rows_out.append([ball, name, typ, side, unit]) + else: + sys.exit(f"unhandled pin {func} ({ball})") + + # kipart numbers units in order of first appearance: banks ascending, + # then Config, then Power. Pin order inside a unit stays as in the CSV. + def unit_key(unit): + if unit.startswith("Bank"): + return (0, int(unit[4:])) + return (1, ["Config", "Power"].index(unit)) + rows_out.sort(key=lambda r: unit_key(r[4])) + out.writerows(rows_out) + + +if __name__ == "__main__": + main() diff --git a/kicad/lib/tools/make_7seg_fp.py b/kicad/lib/tools/make_7seg_fp.py new file mode 100755 index 0000000..197bdc1 --- /dev/null +++ b/kicad/lib/tools/make_7seg_fp.py @@ -0,0 +1,77 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-3.0-or-later +"""Write the footprint for the ARKLED SM410561N 0.56" single digit display. + +Dimensions from the ARKLED specification, page 4/4: body 12.60 x 19.0 mm, +2 x 5 pins on a 2.54 mm pitch, rows 15.24 mm apart, pin diameter 0.51 mm, +pin 1 bottom left (digit upright), numbering counter-clockwise. +Footprint origin = pin 1. + + make_7seg_fp.py OUT.kicad_mod +""" +import sys +import uuid + +NS = uuid.UUID("2f1b6f2e-9a77-4b8e-8f0e-5a3c7e1d2b44") +OUT = sys.argv[1] +W, H, PITCH, ROW = 12.60, 19.0, 2.54, 15.24 +CX, CY = 2 * PITCH, -ROW / 2 # body centre relative to pin 1 + + +def u(*a): + return str(uuid.uuid5(NS, "/".join(map(str, a)))) + + +def f(v): + v = round(v, 4) + return "0" if v == 0 else f"{v:g}" + + +o = ['(footprint "7SegmentLED_0.56in_1Digit_SM410561N"\n\t(version 20241229)\n\t(generator "eboard")\n' + '\t(generator_version "9.0")\n\t(layer "F.Cu")\n' + '\t(descr "0.56 inch single digit 7-segment display, ARKLED SM410561N, ' + 'https://www.lcsc.com/product-detail/C141368.html")\n' + '\t(tags "7 segment LED display 0.56 inch")\n'] + + +def prop(name, val, x, y, layer, hide=False): + o.append(f'\t(property "{name}" "{val}"\n\t\t(at {f(x)} {f(y)} 0)\n\t\t(layer "{layer}")\n' + + ('\t\t(hide yes)\n' if hide else '') + + f'\t\t(uuid "{u("p", name)}")\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1 1)\n' + '\t\t\t\t(thickness 0.15)\n\t\t\t)\n\t\t)\n\t)\n') + + +def line(x1, y1, x2, y2, layer, w): + o.append(f'\t(fp_line\n\t\t(start {f(x1)} {f(y1)})\n\t\t(end {f(x2)} {f(y2)})\n\t\t(stroke\n' + f'\t\t\t(width {w})\n\t\t\t(type solid)\n\t\t)\n\t\t(layer "{layer}")\n' + f'\t\t(uuid "{u("l", layer, x1, y1, x2, y2)}")\n\t)\n') + + +def rect(x1, y1, x2, y2, layer, w): + for a, b in (((x1, y1), (x2, y1)), ((x2, y1), (x2, y2)), ((x2, y2), (x1, y2)), ((x1, y2), (x1, y1))): + line(*a, *b, layer, w) + + +x1, x2, y1, y2 = CX - W / 2, CX + W / 2, CY - H / 2, CY + H / 2 +prop("Reference", "REF**", CX, y1 - 1.5, "F.SilkS") +prop("Value", "SM410561N", CX, y2 + 1.5, "F.Fab") +prop("Datasheet", "https://www.lcsc.com/product-detail/C141368.html", 0, 0, "F.Fab", hide=True) +prop("Description", "0.56 inch single digit 7-segment display", 0, 0, "F.Fab", hide=True) +o.append('\t(attr through_hole)\n') +rect(x1, y1, x2, y2, "F.Fab", 0.1) +rect(x1 - 0.12, y1 - 0.12, x2 + 0.12, y2 + 0.12, "F.SilkS", 0.12) +rect(x1 - 0.5, y1 - 0.5, x2 + 0.5, y2 + 0.5, "F.CrtYd", 0.05) +line(x1 - 0.5, 1.2, x1 - 0.5, -1.2, "F.SilkS", 0.12) # pin 1 marker +o.append(f'\t(fp_text user "${{REFERENCE}}"\n\t\t(at {f(CX)} {f(CY)} 0)\n\t\t(layer "F.Fab")\n' + f'\t\t(uuid "{u("t")}")\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1 1)\n' + '\t\t\t\t(thickness 0.15)\n\t\t\t)\n\t\t)\n\t)\n') +pads = [(n, (n - 1) * PITCH, 0.0) for n in range(1, 6)] + \ + [(n, (10 - n) * PITCH, -ROW) for n in range(6, 11)] +for n, x, y in pads: + shape = "rect" if n == 1 else "circle" + o.append(f'\t(pad "{n}" thru_hole {shape}\n\t\t(at {f(x)} {f(y)})\n\t\t(size 1.5 1.5)\n' + f'\t\t(drill 0.8)\n\t\t(layers "*.Cu" "*.Mask")\n\t\t(remove_unused_layers no)\n' + f'\t\t(uuid "{u("pad", n)}")\n\t)\n') +o.append('\t(embedded_fonts no)\n)\n') +open(OUT, "w").write("".join(o)) +print("wrote", OUT) diff --git a/kicad/lib/tools/make_eboard_lib.sh b/kicad/lib/tools/make_eboard_lib.sh new file mode 100755 index 0000000..1399513 --- /dev/null +++ b/kicad/lib/tools/make_eboard_lib.sh @@ -0,0 +1,62 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-3.0-or-later +# Build kicad/lib/eboard.kicad_sym: +# - symbols generated by kipart from the CSV files in this folder, +# - plus ready-made symbols from the *.kicad_sym files in this folder +# (e.g. the HR911130A symbol from a KiCad library merge request). +# +# kicad/lib/tools/make_eboard_lib.sh +# +# Needs kipart (pipx install kipart). +set -eu +here=$(cd "$(dirname "$0")" && pwd) +command -v kipart >/dev/null 2>&1 || { + echo "kipart not found; install it with: pipx install kipart" >&2 + exit 1 +} +out=$here/../eboard.kicad_sym +tmp=$(mktemp -d) +trap 'rm -rf "$tmp"' EXIT + +kipart -b --bundle-style none -w -o "$tmp/raw.kicad_sym" \ + "$here"/ch347f.csv "$here"/rtl8211f.csv "$here"/sm410561n.csv +python3 -I "$here/kicad_sym_grid.py" "$tmp/raw.kicad_sym" > "$tmp/grid.kicad_sym" + +# append the top-level symbols of the extra libraries +python3 -I - "$tmp/grid.kicad_sym" "$here"/*.kicad_sym > "$out" <<'EOF' +import re, sys + + +def match_paren(t, i): + depth, j = 0, i + while True: + c = t[j] + if c == '"': + j += 1 + while t[j] != '"': + j += 2 if t[j] == "\\" else 1 + elif c == "(": + depth += 1 + elif c == ")": + depth -= 1 + if depth == 0: + return j + 1 + j += 1 + + +base = open(sys.argv[1]).read() +blocks = [] +for path in sys.argv[2:]: + t = open(path).read() + i = t.index("(", 1) + while True: + m = re.compile(r'\(symbol "').search(t, i) + if not m: + break + e = match_paren(t, m.start()) + blocks.append(t[m.start():e]) + i = e +end = base.rstrip().rfind(")") +sys.stdout.write(base[:end] + "".join(" " + b + "\n" for b in blocks) + ")\n") +EOF +echo "wrote $out" diff --git a/kicad/lib/tools/make_ecp5_symbol.sh b/kicad/lib/tools/make_ecp5_symbol.sh new file mode 100755 index 0000000..2495590 --- /dev/null +++ b/kicad/lib/tools/make_ecp5_symbol.sh @@ -0,0 +1,37 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-3.0-or-later +# Generate the LFE5U-25F and LFE5U-45F caBGA256 symbols from the Lattice +# pinout CSVs (FPGA-SC-02033 ECP5U-25, FPGA-SC-02034 ECP5U-45). +# +# kicad/lib/tools/make_ecp5_symbol.sh +# +# Needs kipart (pipx install kipart). +# +# Both parts have the same balls, banks and differential pairs in caBGA256; +# only the pad names and the upper-corner PLL inputs (45F only) differ. +# Writes kicad/lib/eboard_fpga.kicad_sym (overwritten). +set -eu +here=$(cd "$(dirname "$0")" && pwd) +ds=$here/../../../datasheets +command -v kipart >/dev/null 2>&1 || { + echo "kipart not found; install it with: pipx install kipart" >&2 + exit 1 +} +fp=Package_BGA:BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_Ball0.45mm_Pad0.32mm_NSMD +out=$here/../eboard_fpga.kicad_sym +tmp=$(mktemp -d) +trap 'rm -rf "$tmp"' EXIT + +python3 -I "$here/lattice2kipart.py" "$ds/FPGA-SC-02033-2-0-ECP5U-25-Pinout.csv" \ + CABGA256 LFE5U-25F-xBG256x "$fp" 24K > "$tmp/lfe5u25.csv" +python3 -I "$here/lattice2kipart.py" "$ds/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv" \ + CABGA256 LFE5U-45F-xBG256x "$fp" 44K > "$tmp/lfe5u45.csv" +# kipart names the units after the CSV unit column (Bank0 ... Bank8, Config, Power). +kipart -b --bundle-style none -w -o "$tmp/raw.kicad_sym" "$tmp/lfe5u45.csv" +# put all pin ends on the 2.54 mm grid +python3 -I "$here/kicad_sym_grid.py" "$tmp/raw.kicad_sym" > "$tmp/lfe5u45.kicad_sym" +# 25F: same geometry as the 45F symbol, pin names from the 25F pinout, +# so "Change symbol" swaps the two parts without touching any wire. +python3 -I "$here/derive_symbol.py" "$tmp/lfe5u45.kicad_sym" LFE5U-45F-xBG256x \ + "$tmp/lfe5u25.csv" > "$out" +echo "wrote $out" diff --git a/kicad/lib/tools/rtl8211f.csv b/kicad/lib/tools/rtl8211f.csv new file mode 100644 index 0000000..f25b3c3 --- /dev/null +++ b/kicad/lib/tools/rtl8211f.csv @@ -0,0 +1,49 @@ +RTL8211F-CG +Footprint:,Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm_ThermalVias +Datasheet:,https://www.realtek.com/Product/Index?id=3846 +Description:,"Integrated 10/100/1000M Ethernet transceiver, RGMII, internal 1.0V switching regulator, QFN-40 5x5mm" +Source*:,"Realtek RTL8211F(I)-CG/RTL8211FD(I)-CG datasheet Rev. 1.4: pins section 6 tables 1-9, strap functions table 10; EP = pad 41 (GND)" +Keywords:,Ethernet PHY gigabit RGMII Realtek +Filters:,QFN*40*1EP*5x5mm*P0.4mm* +pin,name,type,side +20,TXC,input,left +19,TXCTL,input,left +18,TXD0,input,left +17,TXD1,input,left +16,TXD2,input,left +15,TXD3,input,left +27,RXC/PHYAD1,output,left +26,RXCTL/PHYAD2,output,left +25,RXD0/RXDLY,output,left +24,RXD1/TXDLY,output,left +23,RXD2/PLLOFF,output,left +22,RXD3/PHYAD0,output,left +13,MDC,input,left +14,MDIO,bidirectional,left +31,INTB/PMEB,open_collector,left +12,~{PHYRSTB},input,left +35,CLKOUT,output,left +1,MDIP0,bidirectional,right +2,MDIN0,bidirectional,right +4,MDIP1,bidirectional,right +5,MDIN1,bidirectional,right +6,MDIP2,bidirectional,right +7,MDIN2,bidirectional,right +9,MDIP3,bidirectional,right +10,MDIN3,bidirectional,right +32,LED0/CFG_EXT,bidirectional,right +33,LED1/CFG_LDO0,bidirectional,right +34,LED2/CFG_LDO1,bidirectional,right +36,XTAL_IN,input,right +37,XTAL_OUT,output,right +39,RSET,passive,right +30,REG_OUT,power_out,right +29,DVDD33,power_in,top +28,DVDD_RG,power_in,top +11,AVDD33,power_in,top +40,AVDD33,power_in,top +21,DVDD10,power_in,top +3,AVDD10,power_in,top +8,AVDD10,power_in,top +38,AVDD10,power_in,top +41,GND,power_in,bottom diff --git a/kicad/lib/tools/sm410561n.csv b/kicad/lib/tools/sm410561n.csv new file mode 100644 index 0000000..80aa2e8 --- /dev/null +++ b/kicad/lib/tools/sm410561n.csv @@ -0,0 +1,18 @@ +SM410561N +Footprint:,eboard:7SegmentLED_0.56in_1Digit_SM410561N +Datasheet:,https://www.lcsc.com/product-detail/C141368.html +Description:,"0.56 inch single digit 7-segment LED display, common anode, red, through hole" +Source*:,"ARKLED SM410561N specification (2011-12-08), page 4/4: segment pinout and dimensions" +Keywords:,7 segment display LED common anode +Filters:,7SegmentLED*0.56in* +pin,name,type,side +7,A,passive,left +6,B,passive,left +4,C,passive,left +2,D,passive,left +1,E,passive,left +9,F,passive,left +10,G,passive,left +5,DP,passive,left +3,CA,passive,top +8,CA,passive,top diff --git a/kicad/power.kicad_sch b/kicad/power.kicad_sch new file mode 100644 index 0000000..64bbc71 --- /dev/null +++ b/kicad/power.kicad_sch @@ -0,0 +1,5459 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "252a92d1-26e7-5638-9c79-6454f55fbc78") + (paper "A4") + (title_block + (title "eboard - Power") + (date "2026-11-08") + (rev "0.1") + (comment 1 "CERN-OHL-S-2.0") + ) + (lib_symbols +(symbol "Device:C" +(property "Reference" "C" + (at 0.635 2.54 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) +(property "Value" "C" + (at 0.635 -2.54 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) +(property "Footprint" "" + (at 0.9652 -3.81 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Datasheet" "~" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Description" "Unpolarized capacitor" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_keywords" "cap capacitor" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_fp_filters" "C_*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(pin_numbers + (hide yes) + ) +(pin_names + (offset 0.254) + ) +(exclude_from_sim no) +(in_bom yes) +(on_board yes) +(symbol "C_0_1" + (polyline + (pts + (xy -2.032 0.762) (xy 2.032 0.762) + ) + (stroke + (width 0.508) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -2.032 -0.762) (xy 2.032 -0.762) + ) + (stroke + (width 0.508) + (type default) + ) + (fill + (type none) + ) + ) + ) +(symbol "C_1_1" + (pin passive line + (at 0 3.81 270) + (length 2.794) + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -3.81 90) + (length 2.794) + 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top) + ) + (uuid "fa13effa-da42-55a1-b654-2ea77fe1f420") + ) + (text "VCCAUX 2.5 V (2.375-2.625 V)\nLDO from +3V3, ICCAUX 16 / 17 mA typ. (LFE5U-25F / 45F)\nFerrite + 10 uF + 100 nF per pin at the FPGA (TN-02038)" + (exclude_from_sim no) + (at 114.3 86.36 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "970de273-88c0-5b01-947e-ef3577282a61") + ) + (text "VCCIO, SDRAM, Ethernet PHY, CH347 3.3 V\nVout = 0.6 V * (1 + 15k/3.3k) = 3.33 V" + (exclude_from_sim no) + (at 154.94 127 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "582a8614-2a01-569d-a8a9-67c8c962be40") + ) + (text "Power supply" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "e6bc061f-763c-535c-8b1a-4f678b531481") + ) + (text "+5V comes from the USB-C connector on the USB sheet.\n+1V1 and +3V3: buck converters TLV62569DBV (2 A, SOT-23-5) as on ULX3S. FB = 0.6 V.\nFeedforward C2/C8 100 pF across the upper divider resistor (TI: optional, 6.8 pF with 200k):\nzero at 159 kHz (+1V1, 10k) and 106 kHz (+3V3, 15k).\n+2V5: LDO AP2112K-2.5 from +3V3, so VCCIO (3.3 V) comes up before VCCAUX.\nL1, L2: 2.2 uH SXN SMNR4020-2.2UH, 4x4 mm, Isat 3.4 A (> 3 A switch current limit), 46 mOhm.\nECP5 power-up: no sequencing required, ramp rate 0.01-10 V/ms (DS1044).\nUSB inrush: only C1 + C7 = 9.4 uF sit directly on VBUS (USB limit 10 uF). The buck outputs\ncharge through the 800 us internal soft start. Keep extra capacitance off +5V." + (exclude_from_sim no) + (at 25.4 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "09858c86-7257-5cb6-8e86-818a9864a105") + ) + (symbol + (lib_id "Regulator_Switching:TLV62569DBV") + (at 63.5 50.8 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "4f5adeed-8308-5d0f-9e2e-4bb0e4f7678b") + (property "Reference" "U1" + (at 58.42 44.45 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "TLV62569DBV" + (at 64.77 44.45 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Package_TO_SOT_SMD:SOT-23-5" + (at 63.5 50.8 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "http://www.ti.com/lit/ds/symlink/tlv62569.pdf" + (at 63.5 50.8 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "High Efficiency Synchronous Buck Converter, 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38.1 48.26 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "07ae48e9-dbdf-5a4e-9923-73dccb7c0271") + (property "Reference" "#PWR01" + (at 38.1 52.07 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "+5V" + (at 36.195 43.815 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 38.1 48.26 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 38.1 48.26 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"+5V\"" + (at 38.1 48.26 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "f93585bc-cb09-5a2d-b044-a3d55ca05d1f") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/feacd437-5a41-532e-b95f-5e77b1b2dc10" + (reference "#PWR01") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 45.72 52.07 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "a1afc8b3-6838-5886-b091-763e9dc8f9b8") + (property "Reference" "C1" + (at 48.26 50.8 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "4.7uF" + (at 48.26 53.34 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0805_2012Metric" + (at 45.72 52.07 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 45.72 52.07 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 45.72 52.07 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1779" + (at 45.72 52.07 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL21A475KAQNNNE" + (at 45.72 52.07 0) + (effects + (font + (size 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Net names as on the DE1\n(DRAM_*), plus DRAM_ADDR12 for 32 MB. FPGA banks 7 + 6 (PINPLAN.md); short traces, no series\nresistors on data/address (as on ULX3S)." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "8f8d3ffa-c761-51e6-8d4c-a55f386621cb") + ) + (global_label "DRAM_DQ0" + (shape bidirectional) + (at 160.02 71.12 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "039e9c84-5a1a-571f-aabb-84b6166b646d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 71.12 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ1" + (shape bidirectional) + (at 160.02 73.66 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "de84f646-bcbe-5717-9d48-f76b05a91112") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ2" + (shape bidirectional) + (at 160.02 76.2 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "3ed17329-8016-5471-a389-81a1c0862c61") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 76.2 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ3" + (shape bidirectional) + (at 160.02 78.74 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "b5d40ee0-ee7d-5617-9fdb-5bb3e6e1e3da") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 78.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ4" + (shape bidirectional) + (at 160.02 81.28 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "f537b3c9-64a1-51db-9d22-aafddc0ed379") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 81.28 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ5" + (shape bidirectional) + (at 160.02 83.82 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "116c8aa2-8d52-5a53-9f07-4a54ae47144a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 83.82 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ6" + (shape bidirectional) + (at 160.02 86.36 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "eef894af-e228-5332-a99a-9fc003053435") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 86.36 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ7" + (shape bidirectional) + (at 160.02 88.9 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid 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(fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "a4a195b0-8951-5453-a045-0409c6ae1c62") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 129.54 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_RAS_N" + (shape input) + (at 119.38 132.08 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "30875c4c-fc8c-522f-bbcd-71983418f3d8") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 132.08 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_CS_N" + (shape input) + (at 119.38 114.3 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "bdb6e064-f45a-536f-8ac6-ec5b9b81d480") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 114.3 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_BA_0" + (shape input) + (at 119.38 71.12 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "a7917485-4d3a-5cef-81a8-3d7a3693c9c7") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 71.12 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_BA_1" + (shape input) + (at 119.38 73.66 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "5ed58568-24c2-5b4f-b594-135490b31bef") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 73.66 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR10" + (shape input) + (at 119.38 104.14 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "e430cce0-fc2b-5808-af1b-c36e07add99c") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 104.14 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR0" + (shape input) + (at 119.38 78.74 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "658cd529-d032-5363-a18e-9e6436985a4b") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 78.74 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR1" + (shape input) + (at 119.38 81.28 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "1f7c100c-529d-5b94-ad62-7d0395850ab9") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 81.28 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR2" + (shape input) + (at 119.38 83.82 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "94c1babf-9e86-51af-b440-44905ce69ab0") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 83.82 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR3" + (shape input) + (at 119.38 86.36 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "ad5e76b4-10ab-5e0c-9173-39a2fb65f065") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 86.36 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR4" + (shape input) + (at 119.38 88.9 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d30a0f13-5889-5255-9188-1d7381d66996") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 88.9 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR5" + (shape input) + (at 119.38 91.44 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "b1380d06-9ce0-57e2-bb3e-93557a596503") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 91.44 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR6" + (shape input) + (at 119.38 93.98 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d44d0677-2268-5213-ab8d-5b9be10eed6a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 93.98 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR7" + (shape input) + (at 119.38 96.52 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2bbf73a8-46ad-56d4-a39f-cf20e660306f") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 96.52 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR8" + (shape input) + (at 119.38 99.06 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "ecc7c998-5adf-538e-9397-a805951852ba") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 99.06 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR9" + (shape input) + (at 119.38 101.6 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "7586ce28-b5f3-5238-89c4-8039f10a6bc7") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 101.6 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR11" + (shape input) + (at 119.38 106.68 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2ebb22f7-48c7-5b28-9081-ffdd2924f26d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 106.68 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_ADDR12" + (shape input) + (at 119.38 109.22 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "72ddd3f0-ec03-53a9-8628-8963291cb14e") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 109.22 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_CKE" + (shape input) + (at 119.38 116.84 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "0935d7c8-0da6-5a4f-95dc-0f9fa11378dd") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 116.84 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "SDRAM_CLK" + (at 99.06 119.38 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "dce413af-42f2-5db7-b99b-803f0e447825") + ) + (global_label "DRAM_UDQM" + (shape input) + (at 119.38 124.46 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "1a553cdd-319f-544c-bb46-7e7d380d3d20") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 119.38 124.46 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ8" + (shape bidirectional) + (at 160.02 91.44 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "5f0843d0-ecc1-5b5e-8dbd-9386f1e1a4bb") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 91.44 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ9" + (shape bidirectional) + (at 160.02 93.98 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "961bb43d-5ed8-5d74-a612-b0e09a924d09") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 93.98 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ10" + (shape bidirectional) + (at 160.02 96.52 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "df311c10-0fcc-5373-b5db-003faf721dd0") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 96.52 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ11" + (shape bidirectional) + (at 160.02 99.06 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "bcbcd7f8-ffed-51e3-b386-d868dcfc7b5c") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 160.02 99.06 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "DRAM_DQ12" + (shape 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(symbol + (lib_id "Memory_RAM:MT48LC16M16A2TG") + (at 139.7 101.6 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "72a0491d-29c5-5d1f-9f61-324ba50d7aa4") + (property "Reference" "U9" + (at 142.24 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "W9825G6KH-6" + (at 142.24 66.04 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Package_SO:TSOP-II-54_22.2x10.16mm_P0.8mm" + (at 139.7 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "https://www.winbond.com/hq/product/code-storage-flash-memory/sdram/?__locale=en&partNo=W9825G6KH" + (at 139.7 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "256Mbit (4M x 16 x 4 banks) SDR SDRAM, 166 MHz, 3.3 V, TSOP-II-54; pin compatible with MT48LC16M16A2TG" + (at 139.7 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) 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76.2 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1525" + (at 76.2 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL05B104KO5NNNC" + (at 76.2 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Samsung Electro-Mechanics" + (at 76.2 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "345136ad-dea8-5e53-b37c-b443ef787078") + ) + (pin "2" + (uuid "5c9e1ec4-1c15-5c6e-ae03-61981999569a") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "C68") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 76.2 180.34 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "548afc1d-d6cb-5e38-9d9e-ed37beb19839") + (property "Reference" "#PWR149" + (at 76.2 186.69 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 74.295 184.785 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 76.2 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 76.2 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 76.2 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "a51d88f9-adc7-530b-a4c7-21de25fe3c4d") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "#PWR149") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 88.9 176.53 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "55ab6ae9-a11d-5978-b648-541960161e27") + (property "Reference" "C69" + (at 91.44 175.26 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "100nF" + (at 91.44 177.8 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0402_1005Metric" + (at 88.9 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 88.9 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 88.9 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1525" + (at 88.9 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL05B104KO5NNNC" + (at 88.9 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Samsung Electro-Mechanics" + (at 88.9 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "a667809f-0cd9-5dc9-9a2a-ddd5a63aa060") + ) + (pin "2" + (uuid "3f901bda-8615-540d-90d8-53ccea038e6b") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "C69") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 88.9 180.34 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "2adf0cea-8cc7-5f51-b938-7db7c376d3d5") + (property "Reference" "#PWR150" + (at 88.9 186.69 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 86.995 184.785 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 88.9 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 88.9 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 88.9 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "055bfc82-330c-5999-8a06-a862e8f902f1") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "#PWR150") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 101.6 176.53 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "cd17555b-4998-5b6a-a85e-b0af5e18cda3") + (property "Reference" "C70" + (at 104.14 175.26 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "100nF" + (at 104.14 177.8 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0402_1005Metric" + (at 101.6 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 101.6 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 101.6 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1525" + (at 101.6 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL05B104KO5NNNC" + (at 101.6 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Samsung Electro-Mechanics" + (at 101.6 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "8f819527-10fe-5fab-8483-4f7d4de7e0ef") + ) + (pin "2" + (uuid "8fb9dc73-2b8c-5be5-9067-7a00913ff588") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "C70") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 101.6 180.34 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "1d0d2b5f-ca14-5a9c-8e37-cd234fd96d63") + (property "Reference" "#PWR151" + (at 101.6 186.69 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 99.695 184.785 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 101.6 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 101.6 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 101.6 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "e0f56480-d41f-522b-9e22-ad371308b5d2") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "#PWR151") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 114.3 176.53 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "b459f2e2-bd25-551c-97c2-28932e1da611") + (property "Reference" "C71" + (at 116.84 175.26 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "100nF" + (at 116.84 177.8 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0402_1005Metric" + (at 114.3 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 114.3 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 114.3 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1525" + (at 114.3 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL05B104KO5NNNC" + (at 114.3 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Samsung Electro-Mechanics" + (at 114.3 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "c45b6cc8-889e-55e6-9231-fb14ece9d0d7") + ) + (pin "2" + (uuid "c4b9d0fe-8efb-54e6-800f-d66aa66883fb") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "C71") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 114.3 180.34 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "57534959-6524-5892-ba42-22042fbefd48") + (property "Reference" "#PWR152" + (at 114.3 186.69 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 112.395 184.785 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 114.3 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 114.3 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 114.3 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "d2b7e923-7b4d-51cc-9baf-a68f06fbdbb7") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "#PWR152") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 127 176.53 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "ba1bade4-25e0-591b-ac39-8a121b2d4bba") + (property "Reference" "C72" + (at 129.54 175.26 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "100nF" + (at 129.54 177.8 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0402_1005Metric" + (at 127 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 127 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 127 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C1525" + (at 127 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "CL05B104KO5NNNC" + (at 127 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Samsung Electro-Mechanics" + (at 127 176.53 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "c4595a1c-54d9-5cb1-9598-9ecc7ef846c6") + ) + (pin "2" + (uuid "f7209a7e-fa94-5697-82a5-50b2b072a041") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "C72") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 127 180.34 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "73c1e224-eed3-5a35-8dca-b4f9f1f1890d") + (property "Reference" "#PWR153" + (at 127 186.69 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 125.095 184.785 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 127 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 127 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 127 180.34 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "539949bc-2212-5f00-bafe-a6f17c0f52f3") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/d368b302-2a97-5280-a21d-7ae9380d91e8" + (reference "#PWR153") + (unit 1) + ) + ) + ) + ) + (embedded_fonts no) +) diff --git a/kicad/sym-lib-table b/kicad/sym-lib-table new file mode 100644 index 0000000..491561f --- /dev/null +++ b/kicad/sym-lib-table @@ -0,0 +1,5 @@ +(sym_lib_table + (version 7) + (lib (name "eboard")(type "KiCad")(uri "${KIPRJMOD}/lib/eboard.kicad_sym")(options "")(descr "eboard project symbols")) + (lib (name "eboard_fpga")(type "KiCad")(uri "${KIPRJMOD}/lib/eboard_fpga.kicad_sym")(options "")(descr "ECP5 symbols generated from Lattice pinout CSV")) +) diff --git a/kicad/testpoints.kicad_sch b/kicad/testpoints.kicad_sch new file mode 100644 index 0000000..6292e0a --- /dev/null +++ b/kicad/testpoints.kicad_sch @@ -0,0 +1,3227 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "ae21630b-d69b-5df6-af13-76f404785aa0") + (paper "A4") + (title_block + (title "eboard - Test points") + (date "2026-11-08") + (rev "0.1") + (comment 1 "CERN-OHL-S-2.0") + ) + (lib_symbols +(symbol "Connector:TestPoint" +(property "Reference" "TP" + (at 0 6.858 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Value" "TestPoint" + (at 0 5.08 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Footprint" "" + (at 5.08 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Datasheet" "~" + (at 5.08 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Description" "test point" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_keywords" "test point tp" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_fp_filters" "Pin* Test*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(pin_numbers + (hide yes) + ) +(pin_names + (offset 0.762) + (hide yes) + ) +(exclude_from_sim no) +(in_bom yes) +(on_board yes) +(symbol "TestPoint_0_1" + (circle + (center 0 3.302) + (radius 0.762) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + ) +(symbol "TestPoint_1_1" + (pin passive line + (at 0 0 90) + (length 2.54) + (name "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) +(embedded_fonts no) +) +(symbol "Mechanical:MountingHole_Pad" +(property "Reference" "H" + (at 0 6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Value" "MountingHole_Pad" + (at 0 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Datasheet" "~" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Description" "Mounting Hole with connection" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_keywords" "mounting hole" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_fp_filters" "MountingHole*Pad*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(pin_numbers + (hide yes) + ) +(pin_names + (offset 1.016) + (hide yes) + ) +(exclude_from_sim no) +(in_bom no) +(on_board yes) +(symbol "MountingHole_Pad_0_1" + (circle + (center 0 1.27) + (radius 1.27) + (stroke + (width 1.27) + (type default) + ) + (fill + (type none) + ) + ) + ) +(symbol "MountingHole_Pad_1_1" + (pin input line + (at 0 -2.54 90) + (length 2.54) + (name "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) +(embedded_fonts no) +) +(symbol "power:+1V1" +(property "Reference" "#PWR" + (at 0 -3.81 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Value" "+1V1" + (at 0 3.556 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Datasheet" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Description" "Power symbol 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Further test pads on their sheets: VBUS (USB),\nFPGA_PROGRAMN / FPGA_INITN / FPGA_DONE (FPGA config), ETH_1V0 (Ethernet).\nJTAG: the 1x6 header footprint J2 (USB sheet, not fitted) serves as test access.\nScope ground loops for the lab (Keystone 5011): GPIO sheet." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "f2ec99bd-890e-5b33-9394-8d6826cd9240") + ) + (text "Supply rails" + (exclude_from_sim no) + (at 25.4 55.88 0) + (effects + (font + (size 1.27 1.27) + (bold yes) + ) + (justify left top) + ) + (uuid "bdec99ee-caf7-56b4-9f22-1356e5edcb66") + ) + (text "GND, spread over the board (next to the rail pads, FPGA, Ethernet, GPIO)" + (exclude_from_sim no) + (at 25.4 93.98 0) + (effects + (font + (size 1.27 1.27) + (bold yes) + ) + (justify left top) + ) + (uuid "7f7d45f7-b5d2-5b2a-b85d-8d7f3f96b011") + ) + (text "Signals" + (exclude_from_sim no) + (at 25.4 132.08 0) + (effects + (font + (size 1.27 1.27) + (bold yes) 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of +eboard.kicad_pro, with stable UUIDs, from the code below: + + python3 kicad/tools/gen_sch.py [KICAD_PROJECT_DIR] # default: kicad/ + +WARNING: the schematic is now edited in KiCad. Running this script again +OVERWRITES all sheets and discards every change made in KiCad since then. +It is kept to document how the schematic was created (part choices, LCSC and +MPN table, ball assignment of the FPGA banks), not for regular use. + +Needs the KiCad 9 symbol libraries (KICAD9_SYMBOL_DIR, default +/usr/share/kicad/symbols) and the project libraries in lib/. +""" +import json +import os +import re +import sys +import uuid +from collections import Counter + +OUT = sys.argv[1] if len(sys.argv) > 1 else os.path.dirname(os.path.dirname(os.path.abspath(__file__))) +PROJECT = "eboard" +SYMDIR = os.environ.get("KICAD9_SYMBOL_DIR", "/usr/share/kicad/symbols") +PROJLIBS = {"eboard": os.path.join(OUT, "lib/eboard.kicad_sym"), + "eboard_fpga": os.path.join(OUT, "lib/eboard_fpga.kicad_sym")} +NS = uuid.UUID("6b1c2a52-2f0e-4d8e-9c55-3a0e5b0e0b01") +DATE = "2026-11-08" + + +def uid(*parts): + return str(uuid.uuid5(NS, "/".join(map(str, parts)))) + + +ROOT_UUID = uid("root") + + +def r(v): + return f"{round(v, 4):g}" + + +def esc(s): + return s.replace("\\", "\\\\").replace('"', '\\"').replace("\n", "\\n") + + +# ---------------------------------------------------------------- s-expr helpers +def match_paren(t, i): + """Index after the parenthesis group starting at t[i] == '('.""" + depth, j, n = 0, i, len(t) + while j < n: + c = t[j] + if c == '"': + j += 1 + while t[j] != '"': + j += 2 if t[j] == "\\" else 1 + elif c == "(": + depth += 1 + elif c == ")": + depth -= 1 + if depth == 0: + return j + 1 + j += 1 + raise ValueError("unbalanced") + + +def children(block): + """Top-level child groups of an s-expression group.""" + out, i = [], block.index("(", 1) + while True: + k = block.find("(", i) + if k < 0 or k >= len(block) - 1: + return out + e = match_paren(block, k) + out.append(block[k:e]) + i = e + + +_libcache = {} + + +def lib_text(lib): + if lib not in _libcache: + path = PROJLIBS.get(lib, f"{SYMDIR}/{lib}.kicad_sym") + _libcache[lib] = open(path).read() + return _libcache[lib] + + +def lib_block(lib, name): + t = lib_text(lib) + m = re.search(r'\(symbol "' + re.escape(name) + r'"\s', t) + assert m, (lib, name) + return t[m.start():match_paren(t, m.start())] + + +def resolved(lib, name): + """(block, parent-or-same block) for lib:name.""" + b = lib_block(lib, name) + m = re.search(r'\(extends "([^"]+)"\)', b) + return b, (lib_block(lib, m.group(1)) if m else b), (m.group(1) if m else name) + + +def flat_symbol(lib, name): + b, parent, pname = resolved(lib, name) + props = [c for c in children(b) if c.startswith("(property ")] + rest = [c for c in children(parent) + if not c.startswith("(property ") and not c.startswith("(extends ")] + rest = [c.replace(f'(symbol "{pname}_', f'(symbol "{name}_') for c in rest] + return f'(symbol "{lib}:{name}"\n' + "\n".join(props + rest) + "\n)" + + +def lib_pins(lib, name, unit=None): + _, b, pname = resolved(lib, name) + if unit is not None: + # only the pins of this unit (sub-symbols NAME__x) and common pins (NAME_0_x) + b = "".join(c for c in children(b) + if re.match(r'\(symbol "' + re.escape(pname) + rf'_({unit}|0)_\d+"', c)) + pins = {} + for p in re.finditer(r'\(pin \w+ \w+\s*\(at ([-\d.]+) ([-\d.]+) \d+\).*?' + r'\(name "([^"]*)".*?\(number "([^"]*)"', b, re.S): + pins[p.group(4)] = (float(p.group(1)), float(p.group(2)), p.group(3)) + return pins + + +def lib_props(lib, name): + b = lib_block(lib, name) + return dict(re.findall(r'\(property "([^"]+)" "((?:[^"\\]|\\.)*)"', b)) + + +# Manufacturer part numbers of all LCSC parts (from the JLCPCB parts list, 2026-11-08) +PARTS = { + "C11702": ("0402WGF1001TCE", "UNI-ROYAL"), + "C135262": ("SMNR4020-2.2UH", "SXN"), + "C141368": ("SM410561N", "ARKLED"), + "C141836": ("TLV62569DBVR", "Texas Instruments"), + "C14709": ("BLM18PG121SN1D", "Murata Electronics"), + "C1525": ("CL05B104KO5NNNC", "Samsung Electro-Mechanics"), + "C1532": ("0402B223K500NT", "FH"), + "C1550762": ("LFE5U-25F-7BG256I", "Lattice"), + "C15850": ("CL21A106KAYNNNE", "Samsung Electro-Mechanics"), + "C165948": ("TYPE-C-31-M-12", "HRO"), + "C176945": ("AP2112K-2.5TRG1", "Diodes Incorporated"), + "C1779": ("CL21A475KAQNNNE", "Samsung Electro-Mechanics"), + "C18221627": ("CH347F", "WCH"), + "C187932": ("RTL8211F-CG", "Realtek Semicon"), + "C193402": ("SMF5.0A", "MDD"), + "C1972959": ("TPD2E2U06DRLR", "Texas Instruments"), + "C2286": ("KT-0603R", "Hubei KENTO Elec"), + "C22935": ("0603WAF1004T5E", "UNI-ROYAL"), + "C238127": ("5011", "Keystone"), + "C25092": ("0402WGF220JTCE", "UNI-ROYAL"), + "C25104": ("0402WGF3300TCE", "UNI-ROYAL"), + "C25105": ("0402WGF330JTCE", "UNI-ROYAL"), + "C25117": ("0402WGF4700TCE", "UNI-ROYAL"), + "C25123": ("0402WGF5100TCE", "UNI-ROYAL"), + "C25744": ("0402WGF1002TCE", "UNI-ROYAL"), + "C25792": ("0402WGF4702TCE", "UNI-ROYAL"), + "C25884": ("0402WGF2491TCE", "UNI-ROYAL"), + "C25900": ("0402WGF4701TCE", "UNI-ROYAL"), + "C25905": ("0402WGF5101TCE", "UNI-ROYAL"), + "C269102": ("SMD0805B020TF", "Brightking"), + "C269119": ("SMD1206B110TFT", "Brightking"), + "C2827646": ("TPD4E05U06DQAR", "TECH PUBLIC"), + "C2857673": ("SS-12D07-5", "ROCPU Switches"), + "C2901592": ("SX3M50.000M20F30TNN", "Shenzhen SCTF Elec"), + "C318884": ("TS-1187A-B-A-B", "XKB Connection"), + "C394957": ("CMH201209B2R2MT", "FH"), + "C428493": ("10029449-001RLF", "Amphenol ICC"), + "C45783": ("CL21A226MAQNNNE", "Samsung Electro-Mechanics"), + "C5200276": ("EH254V-12-40P", "XFCN"), + "C5333437": ("A2541HWR-2x6P", "CJT"), + "C54408": ("HR911130A", "HANRUN"), + "C5605": ("74HC14D,653", "Nexperia"), + "C57131": ("1C208000BC0R", "KDS Daishinku"), + "C62246": ("W9825G6KH-6", "Winbond Elec"), + "C8545": ("2N7002", "CJ (Jiangsu Changjing)"), + "C9006": ("X322525MOB4SI", "YXC Crystal Oscillators"), + "C9196": ("1206B102K202NT", "FH"), + "C965805": ("XL-1608SYGC-06", "XINGLIGHT"), + "C97521": ("W25Q128JVSIQ", "Winbond Elec"), + "C1546": ("0402CG101J500NT", "FH"), + "C52923": ("CL05A105KA5NQNC", "Samsung Electro-Mechanics"), + "C1549": ("0402CG180J500NT", "FH"), + "C25756": ("0402WGF1502TCE", "UNI-ROYAL"), + "C25752": ("0402WGF1202TCE", "UNI-ROYAL"), + "C25890": ("0402WGF3301TCE", "UNI-ROYAL"), +} +# Basic parts for passives that are placed without an LCSC number: (symbol, value, footprint) +DEFAULT_LCSC = { + ("C", "100pF", "C_0402_1005Metric"): "C1546", + ("C", "1uF", "C_0402_1005Metric"): "C52923", + ("C", "18pF", "C_0402_1005Metric"): "C1549", + ("C", "100nF", "C_0402_1005Metric"): "C1525", + ("C", "22uF", "C_0805_2012Metric"): "C45783", + ("R", "15k", "R_0402_1005Metric"): "C25756", + ("R", "10k", "R_0402_1005Metric"): "C25744", + ("R", "12k", "R_0402_1005Metric"): "C25752", + ("R", "3.3k", "R_0402_1005Metric"): "C25890", + ("R", "4.7k", "R_0402_1005Metric"): "C25900", + ("R", "1k", "R_0402_1005Metric"): "C11702", +} + + +def part_fields(lib, name, value, fp, fields): + """Add LCSC (passive defaults), MPN and Manufacturer to the instance fields.""" + f = dict(fields or {}) + if "LCSC" not in f and lib == "Device" and name in ("R", "C") and fp: + key = (name, value, fp.split(":")[-1]) + if key in DEFAULT_LCSC: + f["LCSC"] = DEFAULT_LCSC[key] + if f.get("LCSC") in PARTS: + mpn, mfr = PARTS[f["LCSC"]] + f["MPN"], f["Manufacturer"] = mpn, mfr + return f + + +# ---------------------------------------------------------------- sheet model +class Sheet: + def __init__(self, name, file_uuid, path, page, paper="A4"): + self.name, self.file_uuid, self.path, self.page = name, file_uuid, path, page + self.paper = paper + self.symbols, self.wires, self.texts, self.libs = [], [], [], {} + self.labels, self.ncs = [], [] + self.points = Counter() # connection points for junction detection + + def place(self, lib, name, ref, value, x, y, rot=0, fp=None, fields=None, + ref_at=None, val_at=None, hide_val=False, centered=False, dnp=False, unit=None, + mirror=False, datasheet=None, description=None, in_bom=True): + self.libs[f"{lib}:{name}"] = (lib, name) + props = lib_props(lib, name) + fields = part_fields(lib, name, value, fp if fp is not None else props.get("Footprint", ""), fields) + pins = lib_pins(lib, name, unit) + abs_pins = {} + for num, (px, py, pname) in pins.items(): + if mirror: # mirror about the y axis (only used with rot 0) + px = -px + dx, dy = {0: (px, -py), 90: (-py, -px), 180: (-px, py), 270: (py, px)}[rot] + pt = (round(x + dx, 2), round(y + dy, 2)) + abs_pins[num] = pt + abs_pins.setdefault(pname, pt) + for pt in set(abs_pins.values()): # stacked pins count once + self.points[pt] += 1 + power = ref.startswith("#") + ref_at = ref_at or (x + 2.54, y - 1.27) + val_at = val_at or (x + 2.54, y + 1.27) + just = None if centered else "left" + f = [("Reference", ref, ref_at, power, just), + ("Value", value, val_at, hide_val, just), + ("Footprint", fp if fp is not None else props.get("Footprint", ""), (x, y), True, None), + ("Datasheet", datasheet or props.get("Datasheet", ""), (x, y), True, None), + ("Description", description or props.get("Description", ""), (x, y), True, None)] + for k, v in (fields or {}).items(): + f.append((k, v, (x, y), True, None)) + # further library fields (e.g. "Source") are copied as hidden fields + std = {"Reference", "Value", "Footprint", "Datasheet", "Description"} | set(fields or {}) + for k, v in props.items(): + if k not in std and not k.startswith("ki_"): + f.append((k, v, (x, y), True, None)) + self.symbols.append(dict(lib_id=f"{lib}:{name}", ref=ref, x=x, y=y, rot=rot, + fields=f, fangle=rot if rot in (90, 270) else 0, + pins=sorted(set(pins)), dnp=dnp, unit=unit or 1, mirror=mirror, in_bom=in_bom, + uuid=uid(self.name, "sym", ref, unit, x, y))) + return abs_pins + + def wire(self, *pts): + for a, b in zip(pts, pts[1:]): + a = (round(a[0], 2), round(a[1], 2)) + b = (round(b[0], 2), round(b[1], 2)) + self.wires.append((a, b)) + self.points[a] += 1 + self.points[b] += 1 + + def label(self, text, x, y, angle=0, glob=False, shape="bidirectional"): + self.labels.append((text, round(x, 2), round(y, 2), angle, glob, shape)) + self.points[(round(x, 2), round(y, 2))] += 1 + + def pin_label(self, pin, text, angle=0, length=5.08, glob=True, shape="bidirectional"): + """Short wire from a pin, ending in a (global) label.""" + x, y = pin + dx, dy = {0: (length, 0), 180: (-length, 0), 90: (0, -length), 270: (0, length)}[angle] + self.wire(pin, (x + dx, y + dy)) + self.label(text, x + dx, y + dy, angle, glob, shape) + + def nc(self, pin): + self.ncs.append(pin) + + def text(self, s, x, y, size=1.27, bold=False): + self.texts.append((s, x, y, size, bold)) + + # -------------------------------------------------------------- output + def render(self, title, extra=""): + o = ["(kicad_sch\n\t(version 20250114)\n\t(generator \"eeschema\")\n" + "\t(generator_version \"9.0\")\n", + f'\t(uuid "{self.file_uuid}")\n\t(paper "{self.paper}")\n', + "\t(title_block\n" + f'\t\t(title "{title}")\n\t\t(date "{DATE}")\n' + '\t\t(rev "0.1")\n' + '\t\t(comment 1 "CERN-OHL-S-2.0")\n\t)\n', + "\t(lib_symbols\n"] + for key in sorted(self.libs): + o.append(flat_symbol(*self.libs[key]) + "\n") + o.append("\t)\n") + for (x, y), n in sorted(self.points.items()): + if n >= 3: + o.append(f"\t(junction\n\t\t(at {r(x)} {r(y)})\n\t\t(diameter 0)\n" + f"\t\t(color 0 0 0 0)\n\t\t(uuid \"{uid(self.name, 'j', x, y)}\")\n\t)\n") + for (x, y) in self.ncs: + o.append(f"\t(no_connect\n\t\t(at {r(x)} {r(y)})\n\t\t(uuid \"{uid(self.name, 'nc', x, y)}\")\n\t)\n") + for (a, b) in self.wires: + o.append(f"\t(wire\n\t\t(pts\n\t\t\t(xy {r(a[0])} {r(a[1])}) (xy {r(b[0])} {r(b[1])})\n\t\t)\n" + "\t\t(stroke\n\t\t\t(width 0)\n\t\t\t(type default)\n\t\t)\n" + f"\t\t(uuid \"{uid(self.name, 'w', a, b)}\")\n\t)\n") + for (s, x, y, size, bold) in self.texts: + o.append(f'\t(text "{esc(s)}"\n\t\t(exclude_from_sim no)\n\t\t(at {r(x)} {r(y)} 0)\n' + f"\t\t(effects\n\t\t\t(font\n\t\t\t\t(size {size} {size})\n" + + ("\t\t\t\t(bold yes)\n" if bold else "") + + "\t\t\t)\n\t\t\t(justify left top)\n\t\t)\n" + f"\t\t(uuid \"{uid(self.name, 't', s, x, y)}\")\n\t)\n") + for (s, x, y, a, glob, shape) in self.labels: + if glob: + just = "right" if a in (180, 270) else "left" + o.append(f'\t(global_label "{esc(s)}"\n\t\t(shape {shape})\n\t\t(at {r(x)} {r(y)} {a})\n' + "\t\t(fields_autoplaced yes)\n" + f"\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.27 1.27)\n\t\t\t)\n\t\t\t(justify {just})\n\t\t)\n" + f"\t\t(uuid \"{uid(self.name, 'gl', s, x, y)}\")\n" + f"\t\t(property \"Intersheetrefs\" \"${{INTERSHEET_REFS}}\"\n\t\t\t(at {r(x)} {r(y)} {a})\n" + "\t\t\t(effects\n\t\t\t\t(font\n\t\t\t\t\t(size 1.27 1.27)\n\t\t\t\t)\n" + f"\t\t\t\t(justify {just})\n\t\t\t\t(hide yes)\n\t\t\t)\n\t\t)\n\t)\n") + else: + just = "right bottom" if a in (180, 270) else "left bottom" + o.append(f'\t(label "{esc(s)}"\n\t\t(at {r(x)} {r(y)} {a})\n' + "\t\t(fields_autoplaced yes)\n" + f"\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.27 1.27)\n\t\t\t)\n\t\t\t(justify {just})\n\t\t)\n" + f"\t\t(uuid \"{uid(self.name, 'l', s, x, y)}\")\n\t)\n") + o.append(extra) + for s in self.symbols: + o.append(f"\t(symbol\n\t\t(lib_id \"{s['lib_id']}\")\n" + f"\t\t(at {r(s['x'])} {r(s['y'])} {s['rot']})\n" + + ("\t\t(mirror y)\n" if s["mirror"] else "") + + f"\t\t(unit {s['unit']})\n" + "\t\t(exclude_from_sim no)\n" + f"\t\t(in_bom {'yes' if s['in_bom'] else 'no'})\n\t\t(on_board yes)\n" + f"\t\t(dnp {'yes' if s['dnp'] else 'no'})\n\t\t(uuid \"{s['uuid']}\")\n") + for (k, v, (fx, fy), hide, just) in s["fields"]: + o.append(f"\t\t(property \"{k}\" \"{v}\"\n\t\t\t(at {r(fx)} {r(fy)} {s['fangle']})\n" + "\t\t\t(effects\n\t\t\t\t(font\n\t\t\t\t\t(size 1.27 1.27)\n\t\t\t\t)\n" + + (f"\t\t\t\t(justify {just})\n" if just else "") + + ("\t\t\t\t(hide yes)\n" if hide else "") + + "\t\t\t)\n\t\t)\n") + for p in s["pins"]: + o.append(f"\t\t(pin \"{p}\"\n\t\t\t(uuid \"{uid(s['uuid'], 'pin', p)}\")\n\t\t)\n") + o.append(f"\t\t(instances\n\t\t\t(project \"{PROJECT}\"\n" + f"\t\t\t\t(path \"{self.path}\"\n\t\t\t\t\t(reference \"{s['ref']}\")\n" + f"\t\t\t\t\t(unit {s['unit']})\n\t\t\t\t)\n\t\t\t)\n\t\t)\n\t)\n") + if self.page == "1": + o.append("\t(sheet_instances\n\t\t(path \"/\"\n\t\t\t(page \"1\")\n\t\t)\n\t)\n") + o.append("\t(embedded_fonts no)\n)\n") + return "".join(o) + + +# ---------------------------------------------------------------- helpers +C0805 = "Capacitor_SMD:C_0805_2012Metric" +C0402 = "Capacitor_SMD:C_0402_1005Metric" +R0402 = "Resistor_SMD:R_0402_1005Metric" +LED0603 = "LED_SMD:LED_0603_1608Metric" + +cnt = Counter() + + +def ref(prefix): + cnt[prefix] += 1 + return f"{prefix}{cnt[prefix]}" + + +TP_PAD = "TestPoint:TestPoint_Pad_D1.5mm" +TP_LOOP = "TestPoint:TestPoint_Keystone_5010-5014_Multipurpose" + + +def tp_pad(sh, net, x, y, kind="label", glob=False): + """Top-layer test pad (no part, not in the BOM) at pin (x, y). + kind: "rail" = power symbol above (pad hangs down), "gnd" = GND below, + "label" = (global) label below.""" + if kind == "rail": + sh.place("Connector", "TestPoint", ref("TP"), net, x, y, rot=180, fp=TP_PAD, in_bom=False, + ref_at=(x, y + 5.08), val_at=(x, y + 7.62), centered=True) + pwr(sh, net, x, y) + return + sh.place("Connector", "TestPoint", ref("TP"), net, x, y, fp=TP_PAD, in_bom=False, + ref_at=(x + 1.27, y - 5.08), val_at=(x + 1.27, y - 2.54)) + if kind == "gnd": + sh.wire((x, y), (x, y + 2.54)) + pwr(sh, "GND", x, y + 2.54) + else: + sh.wire((x, y), (x, y + 5.08)) + sh.label(net, x, y + 5.08, angle=270, glob=glob, + shape="bidirectional" if not glob else fpga_shape_tp(net)) + + +def fpga_shape_tp(net): + return "input" if net in ("CLOCK_50", "UART_RXD") else "output" + + +def pwr(sh, name, x, y): + cnt["#PWR"] += 1 + n = cnt["#PWR"] + if name == "GND": + return sh.place("power", name, f"#PWR{n:02d}", name, x, y, + ref_at=(x, y + 6.35), val_at=(x - 1.905, y + 4.445)) + if name == "PWR_FLAG": + return sh.place("power", name, f"#FLG{n:02d}", name, x, y, + ref_at=(x, y - 1.905), val_at=(x - 2.54, y - 5.08)) + return sh.place("power", name, f"#PWR{n:02d}", name, x, y, + ref_at=(x, y + 3.81), val_at=(x - 1.905, y - 4.445)) + + +def cap(sh, value, x, ytop, fp=C0805, fields=None): + """Vertical capacitor with pin 1 at (x, ytop).""" + return sh.place("Device", "C", ref("C"), value, x, ytop + 3.81, fp=fp, fields=fields, + ref_at=(x + 2.54, ytop + 2.54), val_at=(x + 2.54, ytop + 5.08)) + + +def res(sh, value, x, ytop, fields=None): + """Vertical resistor with pin 1 at (x, ytop).""" + return sh.place("Device", "R", ref("R"), value, x, ytop + 3.81, fp=R0402, fields=fields, + ref_at=(x + 2.54, ytop + 2.54), val_at=(x + 2.54, ytop + 5.08)) + + +# ---------------------------------------------------------------- power sheet +POWER_SHEET_UUID = uid("sheet", "power") +pw = Sheet("Power", uid("file", "power"), f"/{ROOT_UUID}/{POWER_SHEET_UUID}", "2") + + +def buck(x0, y0, rail, ra, rb, vout_text, gnd_flag=False): + """TLV62569 buck converter as in ULX3S power.sch. U at (x0, y0).""" + yr = y0 - 2.54 # VIN / VOUT rail height + u = pw.place("Regulator_Switching", "TLV62569DBV", ref("U"), "TLV62569DBV", + x0, y0, ref_at=(x0 - 5.08, y0 - 6.35), val_at=(x0 + 1.27, y0 - 6.35), + fields={"LCSC": "C141836"}) + xin = x0 - 25.4 + pwr(pw, "+5V", xin, yr) + # 4.7 uF (TI recommendation): keeps the capacitance on VBUS <= 10 uF (USB inrush limit) + cap(pw, "4.7uF", x0 - 17.78, yr, fields={"LCSC": "C1779"}) + pwr(pw, "GND", x0 - 17.78, yr + 7.62) + pw.wire((xin, yr), (x0 - 17.78, yr), (x0 - 10.16, yr), u["VIN"]) + pw.wire(u["EN"], (x0 - 10.16, y0), (x0 - 10.16, yr)) + pwr(pw, "GND", *u["GND"]) + if gnd_flag: + f = (xin - 7.62, y0 + 7.62) + pwr(pw, "PWR_FLAG", *f) + pw.wire(f, (f[0], f[1] + 5.08)) + pwr(pw, "GND", f[0], f[1] + 5.08) + xl = x0 + 19.05 + lp = pw.place("Device", "L", ref("L"), "2.2uH", xl, yr, rot=90, + fp="Inductor_SMD:L_Sunlord_SWPA4020S", + ref_at=(xl, yr - 5.08), val_at=(xl, yr - 2.54), centered=True, + fields={"LCSC": "C135262", "MPN": "SXN SMNR4020-2.2UH"}) + pw.wire(u["SW"], lp["1"]) + xo = lp["2"][0] + xd = xo + 7.62 + res(pw, ra, xd, yr) + res(pw, rb, xd, yr + 7.62) + pwr(pw, "GND", xd, yr + 15.24) + xff = xd + 10.16 + cap(pw, "100pF", xff, yr, fp=C0402) + yfb = yr + 7.62 + pw.wire(u["FB"], (x0 + 10.16, y0), (x0 + 10.16, yfb), (xd, yfb)) + pw.wire((xd, yfb), (xff, yfb)) + xc1, xc2 = xff + 12.7, xff + 22.86 + cap(pw, "22uF", xc1, yr) + cap(pw, "22uF", xc2, yr) + pwr(pw, "GND", xc1, yr + 7.62) + pwr(pw, "GND", xc2, yr + 7.62) + xflag, xend = xc2 + 10.16, xc2 + 20.32 + pw.wire(lp["2"], (xd, yr), (xff, yr), (xc1, yr), (xc2, yr), (xflag, yr), (xend, yr)) + pwr(pw, "PWR_FLAG", xflag, yr) + pwr(pw, rail, xend, yr) + pw.text(vout_text, xend + 7.62, yr - 2.54) + + +def ldo(x0, y0): + """VCCAUX 2.5 V: AP2112K-2.5 LDO fed from +3V3 (ICCAUX 17 mA typ. for LFE5U-45F).""" + yr = y0 - 2.54 + u = pw.place("Regulator_Linear", "AP2112K-2.5", ref("U"), "AP2112K-2.5", + x0, y0, ref_at=(x0 - 5.08, y0 - 6.35), val_at=(x0 + 1.27, y0 - 6.35), + fields={"LCSC": "C176945"}) + xin = x0 - 25.4 + pwr(pw, "+3V3", xin, yr) + cap(pw, "1uF", x0 - 17.78, yr, fp=C0402) + pwr(pw, "GND", x0 - 17.78, yr + 7.62) + pw.wire((xin, yr), (x0 - 17.78, yr), (x0 - 10.16, yr), u["VIN"]) + pw.wire(u["EN"], (x0 - 10.16, y0), (x0 - 10.16, yr)) + pwr(pw, "GND", *u["GND"]) + pw.nc(u["NC"]) + xo = u["VOUT"][0] + xc, xend = xo + 12.7, xo + 35.56 + cap(pw, "1uF", xc, yr, fp=C0402) + pwr(pw, "GND", xc, yr + 7.62) + pw.wire(u["VOUT"], (xc, yr), (xend, yr)) + pwr(pw, "+2V5", xend, yr) + pw.text("VCCAUX 2.5 V (2.375-2.625 V)\nLDO from +3V3, ICCAUX 16 / 17 mA typ. (LFE5U-25F / 45F)\n" + "Ferrite + 10 uF + 100 nF per pin at the FPGA (TN-02038)", xend + 7.62, yr - 2.54) + + +bx = 63.5 +buck(bx, 50.8, "+1V1", "10k", "12k", + "VCC FPGA core 1.1 V\nVout = 0.6 V * (1 + 10k/12k) = 1.10 V", gnd_flag=True) +ldo(bx, 91.44) +buck(bx, 132.08, "+3V3", "15k", "3.3k", + "VCCIO, SDRAM, Ethernet PHY, CH347 3.3 V\nVout = 0.6 V * (1 + 15k/3.3k) = 3.33 V") + +pw.text("Power supply", 25.4, 20.32, size=2.54, bold=True) +pw.text("+5V comes from the USB-C connector on the USB sheet.\n" + "+1V1 and +3V3: buck converters TLV62569DBV (2 A, SOT-23-5) as on ULX3S. FB = 0.6 V.\n" + "Feedforward C2/C8 100 pF across the upper divider resistor (TI: optional, 6.8 pF with 200k):\n" + "zero at 159 kHz (+1V1, 10k) and 106 kHz (+3V3, 15k).\n" + "+2V5: LDO AP2112K-2.5 from +3V3, so VCCIO (3.3 V) comes up before VCCAUX.\n" + "L1, L2: 2.2 uH SXN SMNR4020-2.2UH, 4x4 mm, Isat 3.4 A (> 3 A switch current limit), 46 mOhm.\n" + "ECP5 power-up: no sequencing required, ramp rate 0.01-10 V/ms (DS1044).\n" + "USB inrush: only C1 + C7 = 9.4 uF sit directly on VBUS (USB limit 10 uF). The buck outputs\n" + "charge through the 800 us internal soft start. Keep extra capacitance off +5V.", + 25.4, 160.02) + +# ---------------------------------------------------------------- USB sheet +USB_SHEET_UUID = uid("sheet", "usb") +us = Sheet("USB", uid("file", "usb"), f"/{ROOT_UUID}/{USB_SHEET_UUID}", "3") + +# USB-C receptacle (USB 2.0, 16 pin) +j = us.place("Connector", "USB_C_Receptacle_USB2.0_16P", ref("J"), "USB_C", 40.64, 88.9, + fp="Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12", + ref_at=(30.48, 63.5), val_at=(30.48, 66.04), fields={"LCSC": "C165948"}) +pwr(us, "GND", *j["A1"]) +pwr(us, "GND", *j["S1"]) +# VBUS -> PTC fuse -> +5V +vb = j["A4"] +f1 = us.place("Device", "Polyfuse", ref("F"), "1.1A", 68.58, vb[1], rot=90, + fp="Fuse:Fuse_1206_3216Metric", ref_at=(68.58, vb[1] - 5.08), + val_at=(68.58, vb[1] - 2.54), centered=True, + fields={"LCSC": "C269119", "MPN": "SMD1206B110TFT"}) +xm = round(round((vb[0] + f1["1"][0]) / 2 / 1.27) * 1.27, 2) +us.wire(vb, (xm, vb[1]), f1["1"]) +us.place("Connector", "TestPoint", ref("TP"), "VBUS", xm, vb[1], fp=TP_PAD, in_bom=False, + ref_at=(xm - 6.35, vb[1] - 5.08), val_at=(xm - 6.35, vb[1] - 2.54)) +us.wire(f1["2"], (83.82, vb[1]), (93.98, vb[1])) +pwr(us, "PWR_FLAG", 83.82, vb[1]) +pwr(us, "+5V", 93.98, vb[1]) +# TVS behind the PTC: clamps ESD on VBUS; a permanent overvoltage trips F1 +xt = 99.06 +us.wire((93.98, vb[1]), (xt, vb[1])) +tv = us.place("Device", "D_Zener", ref("D"), "SMF5.0A", xt, vb[1] + 3.81, rot=270, + fp="Diode_SMD:D_SOD-123F", ref_at=(xt + 6.35, vb[1] + 2.54), val_at=(xt + 8.89, vb[1] + 5.08), + centered=True, + fields={"LCSC": "C193402"}, description="TVS diode, unidirectional, 5 V stand-off, 9.2 V clamping, 200 W") +pwr(us, "GND", *tv["2"]) +# CC pull-downs 5.1k (one per CC pin, sink / UFP) +cc1, cc2 = j["A5"], j["B5"] +us.wire(cc1, (86.36, cc1[1])) +res(us, "5.1k", 86.36, cc1[1], fields={"LCSC": "C25905"}) +pwr(us, "GND", 86.36, cc1[1] + 7.62) +us.wire(cc2, (78.74, cc2[1])) +res(us, "5.1k", 78.74, cc2[1], fields={"LCSC": "C25905"}) +pwr(us, "GND", 78.74, cc2[1] + 7.62) +# D- (A7, B7) and D+ (A6, B6) +for a, b, name in (("A7", "B7", "USB_D-"), ("A6", "B6", "USB_D+")): + pa, pb = j[a], j[b] + us.wire(pb, (58.42, pb[1]), (58.42, pa[1])) + us.wire(pa, (58.42, pa[1]), (63.5, pa[1])) + us.label(name, 63.5, pa[1]) +us.nc(j["A8"]) +us.nc(j["B8"]) + +# ESD protection, < 2 pF as required by WCH +e = us.place("Power_Protection", "TPD2E2U06DRL", ref("U"), "TPD2E2U06DRL", 45.72, 137.16, + ref_at=(36.83, 127.0), val_at=(36.83, 129.54), fields={"LCSC": "C1972959"}) +us.pin_label(e["3"], "USB_D+", angle=180, glob=False) +us.pin_label(e["5"], "USB_D-", angle=180, glob=False) +pwr(us, "GND", *e["4"]) +us.nc(e["1"]) +us.nc(e["2"]) + +# CH347F +X, Y = 160.02, 101.6 +u = us.place("eboard", "CH347F", ref("U"), "CH347F", X, Y, + ref_at=(X + 7.62, Y - 33.02), val_at=(X + 7.62, Y - 30.48), + fields={"LCSC": "C18221627"}) +# supply: VCC and VIO on +3V3, 0.1 uF each +yr = 60.96 +us.wire(u["21"], (u["21"][0], yr)) +us.wire(u["6"], (u["6"][0], yr)) +us.wire((129.54, yr), (137.16, yr), (147.32, yr), (u["21"][0], yr), (u["6"][0], yr)) +pwr(us, "+3V3", 129.54, yr) +cap(us, "100nF", 137.16, yr, fp=C0402) +cap(us, "100nF", 147.32, yr, fp=C0402) +pwr(us, "GND", 137.16, yr + 7.62) +pwr(us, "GND", 147.32, yr + 7.62) +# ground (pin 20 and exposed pad = datasheet pin 0 = footprint pad 29) +us.wire(u["29"], u["20"]) +pwr(us, "GND", *u["20"]) +# USB data +us.pin_label(u["28"], "USB_D+", angle=180, length=7.62, glob=False) +us.pin_label(u["27"], "USB_D-", angle=180, length=7.62, glob=False) +# 8 MHz crystal (C57131, CL = 12 pF) with 2 x 18 pF: C = 2 * (CL - ~3 pF stray) +xc, yc = 99.06, 121.92 +y1 = us.place("Device", "Crystal_GND24", ref("Y"), "8MHz", xc, yc, + fp="Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm", + ref_at=(xc, yc - 5.08), val_at=(xc, yc - 2.54), centered=True, + fields={"LCSC": "C57131", "MPN": "KDS 1C208000BC0R"}) +pwr(us, "GND", *y1["2"]) +xi, xo = y1["1"], y1["3"] +xci, xco = xi[0] - 5.08, xo[0] + 5.08 +us.wire(xi, (xci, yc)) +us.wire(xo, (xco, yc)) +cap(us, "18pF", xci, yc, fp=C0402) +cap(us, "18pF", xco, yc, fp=C0402) +pwr(us, "GND", xci, yc + 7.62) +pwr(us, "GND", xco, yc + 7.62) +us.wire((xci, yc), (xci, u["1"][1]), u["1"]) +us.wire((xco, yc), (xco, u["2"][1]), u["2"]) +# reset: 4.7k pull-up to VIO, 100 nF to GND (optional parts in WCH reference) +rst = u["3"] +xr, xrc = 124.46, 81.28 +us.wire(rst, (xr, rst[1]), (xrc, rst[1])) +res(us, "4.7k", xr, rst[1] - 7.62) +pwr(us, "+3V3", xr, rst[1] - 7.62) +cap(us, "100nF", xrc, rst[1], fp=C0402) +pwr(us, "GND", xrc, rst[1] + 7.62) +# ACT LED: on when USB is configured (ACT is active low) +act = u["8"] +yl = 137.16 +us.wire(act, (129.54, act[1]), (129.54, yl)) +led = us.place("Device", "LED", ref("D"), "green", 125.73, yl, rot=180, fp=LED0603, + ref_at=(125.73, yl + 5.08), val_at=(125.73, yl + 2.54), centered=True, + fields={"LCSC": "C965805"}) +rl = us.place("Device", "R", ref("R"), "1k", 118.11, yl, rot=90, fp=R0402, + ref_at=(118.11, yl + 5.08), val_at=(118.11, yl + 2.54), centered=True) +pwr(us, "+3V3", *rl["1"]) + +# signals to the FPGA (global labels, named like the LPF ports later) +# DE1 convention: UART_TXD = FPGA transmits (-> CH347 RXD), UART_RXD = FPGA receives. +# Only UART0 TXD/RXD go to the FPGA (pin budget, see kicad/PINPLAN.md). +SIG = [("19", "UART_RXD", "output"), ("22", "UART_TXD", "input"), + ("23", "JTAG_TCK", "output"), ("26", "JTAG_TMS", "output"), + ("25", "JTAG_TDI", "output"), ("24", "JTAG_TDO", "input")] +for num, name, shape in SIG: + us.pin_label(u[num], name, shape=shape) +for num in ("17", "11", "12", "7", "9", "14", "13", "16", "15", # unused: CTS, I2C, SCS1, TRST, SPI + "18", "10", "4", "5"): # RTS0, DTR0, UART1 + us.nc(u[num]) + +# JTAG pull resistors, ECP5 hardware checklist TN-02038: 4.7k to VCCIO8 (= +3V3) +x = 208.28 +for name, up in (("JTAG_TDI", True), ("JTAG_TMS", True), ("JTAG_TDO", True), ("JTAG_TCK", False)): + res(us, "4.7k", x, 147.32) + if up: + pwr(us, "+3V3", x, 147.32) + us.wire((x, 154.94), (x, 160.02)) + us.label(name, x, 160.02, angle=270, glob=True) + else: + us.wire((x, 147.32), (x, 142.24)) + us.label(name, x, 142.24, angle=90, glob=True) + pwr(us, "GND", x, 154.94) + x += 10.16 + +# JTAG header for an external programmer (not fitted by default) +h = us.place("Connector_Generic", "Conn_01x06", ref("J"), "JTAG", 264.16, 101.6, + fp="Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical", + ref_at=(261.62, 91.44), val_at=(261.62, 93.98), dnp=True) +xh = 251.46 +us.wire(h["1"], (xh, h["1"][1])) +pwr(us, "+3V3", xh, h["1"][1]) +for num, name in (("2", "JTAG_TCK"), ("3", "JTAG_TDI"), ("4", "JTAG_TDO"), ("5", "JTAG_TMS")): + us.pin_label(h[num], name, angle=180, length=7.62) +us.wire(h["6"], (xh, h["6"][1])) +pwr(us, "GND", xh, h["6"][1]) + +us.text("USB-C, CH347F USB to JTAG / UART", 25.4, 20.32, size=2.54, bold=True) +us.text("USB device (sink): CC1 and CC2 each 5.1k to GND -> 5 V from any USB-C host.\n" + "F1: PTC 1.1 A hold / 2.2 A trip protects host and board against shorts.\n" + "TVS SMF5.0A behind F1 clamps ESD on VBUS; a permanent overvoltage makes it conduct and trips F1.\n" + "No series resistors on D+/D- (built into CH347). ESD part < 2 pF (WCH).\n" + "CH347F works without mode straps; used here: UART0 (TXD/RXD) + JTAG. UART1, modem lines,\n" + "SPI and I2C are not connected (FPGA pin budget, see PINPLAN.md).\n" + "VIO = 3.3 V = VCCIO of the FPGA banks the signals go to (JTAG: VCCIO8).\n" + "Names as on the DE1, seen from the FPGA: UART_TXD = FPGA transmits, UART_RXD = FPGA receives.", + 25.4, 160.02) +us.text("JTAG pull resistors\n(ECP5 TN-02038)", 208.28, 132.08) +us.text("not fitted (DNP)", 254.0, 116.84) + + +# ---------------------------------------------------------------- FPGA power sheet +FPWR_SHEET_UUID = uid("sheet", "fpga_power") +fpw = Sheet("FPGA power", uid("file", "fpga_power"), f"/{ROOT_UUID}/{FPWR_SHEET_UUID}", "4") +FPGA = ("eboard_fpga", "LFE5U-25F-xBG256x") +FPGA_REF = ref("U") +C10U = {"LCSC": "C15850"} +C100N = {"LCSC": "C1525"} + + +def cap_row(sh, rail_y, xs, values): + """Capacitors hanging from a horizontal rail at rail_y, GND below.""" + for x, v in zip(xs, values): + if v == "10uF": + cap(sh, v, x, rail_y, fp=C0805, fields=C10U) + elif v == "22uF": + cap(sh, v, x, rail_y, fp=C0805, fields={"LCSC": "C45783"}) + else: + cap(sh, v, x, rail_y, fp=C0402, fields=C100N) + pwr(sh, "GND", x, rail_y + 7.62) + + +# FPGA power unit: VCC (6 balls), VCCAUX (2 balls), GND (27 balls), stacked pins +X, Y = 147.32, 104.14 +u = fpw.place(*FPGA, FPGA_REF, "LFE5U-25F-7BG256I", X, Y, unit=9, + ref_at=(X + 5.08, Y - 2.54), val_at=(X + 5.08, Y), + fields={"LCSC": "C1550762"}) +pwr(fpw, "GND", *u["GND"]) + +# VCC 1.1 V: 3 x 10 uF + 100 nF per pin (6), TN-02038 Table 3.1 +yv = 63.5 +xs = [33.02 + 12.7 * i for i in range(9)] +fpw.wire(u["VCC"], (u["VCC"][0], yv)) +fpw.wire((25.4, yv), *[(x, yv) for x in xs], (u["VCC"][0], yv)) +pwr(fpw, "+1V1", 25.4, yv) +cap_row(fpw, yv, xs, ["10uF"] * 3 + ["100nF"] * 6) +fpw.text("VCC 1.1 V core: 3 x 10 uF + 100 nF per VCC ball (G6 G7 G9 L8 L9 L10)", 33.02, yv - 8.89) + +# VCCAUX 2.5 V: 120 ohm ferrite + 10 uF + 100 nF per pin (2) +ya = 76.2 +fpw.wire(u["VCCAUX"], (u["VCCAUX"][0], ya)) +xa = [162.56, 175.26, 187.96] +fb = fpw.place("Device", "FerriteBead", ref("FB"), "120R@100MHz", 207.01, ya, rot=90, + fp="Inductor_SMD:L_0603_1608Metric", + ref_at=(207.01, ya - 5.08), val_at=(207.01, ya - 2.54), centered=True, + fields={"LCSC": "C14709", "MPN": "BLM18PG121SN1D"}) +fpw.wire((u["VCCAUX"][0], ya), (152.4, ya), *[(x, ya) for x in xa], (195.58, ya), fb["1"]) +fpw.label("FPGA_VCCAUX", 152.4, ya) +pwr(fpw, "PWR_FLAG", 195.58, ya) +fpw.wire(fb["2"], (218.44, ya)) +pwr(fpw, "+2V5", 218.44, ya) +cap_row(fpw, ya, xa, ["10uF", "100nF", "100nF"]) +fpw.text("VCCAUX 2.5 V: ferrite + 10 uF\n+ 100 nF per VCCAUX ball (G11 L7)", 162.56, ya - 11.43) + +# VCCIO decoupling, all banks at 3.3 V. The VCCIO balls are on the bank units. +def vccio_row(yio, banks): + x = 38.1 + xs, vals = [], [] + for bank, balls, n in banks: + fpw.text(f"Bank{bank}\n{balls}", x - 1.27, yio - 8.89) + for v in ["10uF"] + ["100nF"] * n: + xs.append(x) + vals.append(v) + x += 12.7 + fpw.wire((25.4, yio), *[(xx, yio) for xx in xs]) + pwr(fpw, "+3V3", 25.4, yio) + cap_row(fpw, yio, xs, vals) + + +vccio_row(130.81, [("0", "F6 F7", 2), ("1", "F10 F11", 2), ("2", "H11 J11", 2), ("3", "K11 L11", 2)]) +vccio_row(163.83, [("6", "J6 J7", 2), ("7", "H6 H7", 2), ("8", "L6", 1)]) + +fpw.text("FPGA power", 25.4, 20.32, size=2.54, bold=True) +fpw.text("Decoupling per Lattice FPGA-TN-02038 (ECP5 hardware checklist) Table 3.1.\n" + "Place the 100 nF capacitors next to their balls, on the bottom side under the BGA.\n" + "VCCIO: 10 uF + 100 nF per ball for every bank; all banks run at 3.3 V\n" + "(VCCIO8 = 3.3 V also sets the JTAG and configuration levels).\n" + "POR needs VCC >= 0.9 V, VCCAUX >= 2.0 V, VCCIO8 >= 0.95 V.", + 25.4, 27.94) +fpw.text("U6: LFE5U-25F-7BG256I (24K LUTs, JLCPCB C1550762).\n" + "Drop-in: LFE5U-45F-xBG256x (44K LUTs), same balls, banks and differential pairs;\n" + "swap with 'Change symbol'. The 45F has 2 extra PLLs (upper corners): their inputs\n" + "B1 B2 A2 B3 B14 A15 B15 B16 are plain I/O on the 25F -> no clocks on these balls.", + 152.4, 27.94) +fpw.text("VCCIO decoupling (+3V3), 10 uF + 100 nF per ball", 25.4, 114.3) + + +# ---------------------------------------------------------------- FPGA configuration sheet +FCFG_SHEET_UUID = uid("sheet", "fpga_config") +cf = Sheet("FPGA config", uid("file", "fpga_config"), f"/{ROOT_UUID}/{FCFG_SHEET_UUID}", "5") +R4K7 = {"LCSC": "C25900"} +R10K = {"LCSC": "C25744"} +R1K = {"LCSC": "C11702"} +R33 = {"LCSC": "C25105"} +LED_GREEN = {"LCSC": "C965805"} + + +def hres(sh, value, x, y, fields=None): + """Horizontal resistor centred at (x, y); returns pins.""" + return sh.place("Device", "R", ref("R"), value, x, y, rot=90, fp=R0402, fields=fields, + ref_at=(x, y - 5.08), val_at=(x, y - 2.54), centered=True) + + +# Config unit: dedicated configuration and JTAG pins +X, Y = 76.2, 63.5 +c = cf.place(*FPGA, FPGA_REF, "LFE5U-25F-7BG256I", X, Y, unit=8, + ref_at=(X - 17.78, Y - 12.7), val_at=(X - 17.78, Y - 15.24), + fields={"LCSC": "C1550762"}) +for num, name in (("M10", "JTAG_TDO"), ("T10", "JTAG_TCK"), ("R11", "JTAG_TDI"), ("T11", "JTAG_TMS")): + cf.pin_label(c[num], name, shape="input" if name != "JTAG_TDO" else "output") +for num, name in (("T9", "FPGA_INITN"), ("N9", "FPGA_MCLK"), ("R9", "FPGA_PROGRAMN"), + ("P9", "FPGA_DONE"), ("P10", "FPGA_CFG1")): + cf.pin_label(c[num], name, angle=180, length=10.16, glob=False) +# CFG[2:0] = 010: master SPI (MSPI) boot from the flash +cf.wire(c["R10"], (45.72, c["R10"][1])) +cf.wire(c["N10"], (45.72, c["N10"][1])) +cf.wire((45.72, c["R10"][1]), (45.72, c["N10"][1]), (45.72, c["N10"][1] + 5.08)) +pwr(cf, "GND", 45.72, c["N10"][1] + 5.08) + +# pull resistors to VCCIO8 = +3V3 (TN-02038 Table 6.2) +pulls = [("FPGA_PROGRAMN", "4.7k", R4K7), ("FPGA_INITN", "4.7k", R4K7), ("FPGA_DONE", "4.7k", R4K7), + ("FPGA_CFG1", "4.7k", R4K7), ("FLASH_CS", "4.7k", R4K7), ("FLASH_CLK", "1k", R1K), + ("FLASH_IO2", "10k", R10K), ("FLASH_IO3", "10k", R10K)] +for i, (name, val, f) in enumerate(pulls): + x = 129.54 + 12.7 * i + res(cf, val, x, 68.58, fields=f) + pwr(cf, "+3V3", x, 68.58) + cf.wire((x, 76.2), (x, 81.28)) + cf.label(name, x, 81.28, angle=270) +cf.text("Pull-ups to VCCIO8 (TN-02038 Table 6.2).\nFLASH_CS and FLASH_CLK pull-ups next to the flash.", + 129.54, 55.88) + +# MCLK series resistor next to the FPGA (22-80 ohm) +rm = hres(cf, "33", 162.56, 45.72, fields=R33) +cf.wire(rm["1"], (rm["1"][0] - 5.08, 45.72)) +cf.label("FPGA_MCLK", rm["1"][0] - 5.08, 45.72, angle=180) +cf.wire(rm["2"], (rm["2"][0] + 5.08, 45.72)) +cf.label("FLASH_CLK", rm["2"][0] + 5.08, 45.72) +cf.text("MCLK series R close to the FPGA ball N9", 147.32, 35.56) + +# Bank 8: shared configuration pins of the SPI flash (quad SPI capable) +X, Y = 88.9, 116.84 +b8 = cf.place(*FPGA, FPGA_REF, "LFE5U-25F-7BG256I", X, Y, unit=7, + ref_at=(X + 5.08, Y - 22.86), val_at=(X + 5.08, Y - 20.32)) +pwr(cf, "+3V3", *b8["L6"]) +for num, name, ang in (("T8", "FLASH_IO0", 0), ("N8", "FLASH_CS", 0), + ("T7", "FLASH_IO1", 180), ("M7", "FLASH_IO2", 180), ("N7", "FLASH_IO3", 180)): + cf.pin_label(b8[num], name, angle=ang, length=7.62, glob=False) +B8_FREE = {"T6": ("LEDG0", 180), "R7": ("LEDG1", 0), "R6": ("LEDG2", 180), "P7": ("LEDG3", 0), + "R8": ("LEDG4", 180), "P8": ("LEDG5", 0), "M8": ("HEX3_5", 180), "M9": ("HEX3_6", 0)} +for num, (name, _) in B8_FREE.items(): + side = 180 if b8[num][0] < X else 0 + cf.pin_label(b8[num], name, angle=side, length=7.62 if side == 180 else 25.4, shape="output") +cf.text("Bank 8 (VCCIO8 = 3.3 V): SPI flash; the other bank 8 I/O drive LEDG[5:0]\n" + "and HEX3[6:5] (they may toggle during configuration).", + 45.72, 139.7) + +# SPI flash, 16 MB: bitstream (25F ~0.7 MB, 45F ~1.2 MB) + firmware / data +X, Y = 215.9, 116.84 +fl = cf.place("Memory_Flash", "W25Q128JVS", ref("U"), "W25Q128JVSIQ", X, Y, + ref_at=(X + 2.54, Y - 15.24), val_at=(X + 2.54, Y + 15.24), + fields={"LCSC": "C97521"}) +for num, name in (("1", "FLASH_CS"), ("6", "FLASH_CLK"), ("5", "FLASH_IO0"), ("2", "FLASH_IO1"), + ("3", "FLASH_IO2"), ("7", "FLASH_IO3")): + cf.pin_label(fl[num], name, angle=180, length=7.62, glob=False) +P = (X, Y - 17.78) +cf.wire(fl["8"], P, (X + 7.62, P[1])) +pwr(cf, "+3V3", *P) +cap(cf, "100nF", X + 7.62, P[1], fp=C0402, fields=C100N) +pwr(cf, "GND", X + 7.62, P[1] + 7.62) +pwr(cf, "GND", *fl["4"]) + +# PROGRAM button: reloads the bitstream from the flash +sw = cf.place("Switch", "SW_Push", ref("SW"), "TS-1187A", 40.64, 160.02, rot=90, + fp="Button_Switch_SMD:SW_Push_1P1T_XKB_TS-1187A", + ref_at=(46.99, 158.75), val_at=(53.34, 161.29), fields={"LCSC": "C318884", "MPN": "XKB TS-1187A-B-A-B"}) +top, bot = sorted((sw["1"], sw["2"]), key=lambda p: p[1]) +cf.wire(top, (top[0], top[1] - 5.08)) +cf.label("FPGA_PROGRAMN", top[0], top[1] - 5.08, angle=90) +pwr(cf, "GND", *bot) +cf.text("PROG button", 45.72, 163.83) + +# DONE LED: on when the FPGA is configured (DONE is open drain, high = done) +qx, qy = 88.9, 172.72 +q = cf.place("Transistor_FET", "2N7002", ref("Q"), "2N7002", qx, qy, + ref_at=(qx + 5.08, qy - 1.27), val_at=(qx + 5.08, qy + 1.27), fields={"LCSC": "C8545"}) +cf.wire(q["G"], (qx - 10.16, qy)) +cf.label("FPGA_DONE", qx - 10.16, qy, angle=180) +pwr(cf, "GND", *q["S"]) +xd = q["D"][0] +cf.place("Device", "LED", ref("D"), "green", xd, q["D"][1] - 3.81, rot=90, fp=LED0603, + ref_at=(xd - 10.16, q["D"][1] - 5.08), val_at=(xd - 10.16, q["D"][1] - 2.54), fields=LED_GREEN) +res(cf, "1k", xd, q["D"][1] - 15.24, fields=R1K) +pwr(cf, "+3V3", xd, q["D"][1] - 15.24) +cf.text("DONE LED", qx - 25.4, 154.94) + +# 50 MHz oscillator -> PCLK input (planned: M1 = PCLKT6_0, bank 6) +ox, oy = 139.7, 160.02 +xo = cf.place("Oscillator", "ASE-xxxMHz", ref("X"), "SX3M50.000M20F30TNN", ox, oy, + fp="Oscillator:Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm", + ref_at=(ox + 3.81, oy - 8.89), val_at=(ox + 3.81, oy + 8.89), + fields={"LCSC": "C2901592", "MPN": "SX3M50.000M20F30TNN"}) +P = (ox, oy - 10.16) +cf.wire(xo["4"], P, (ox - 10.16, P[1]), (ox - 17.78, P[1])) +cf.wire((ox - 10.16, P[1]), (ox - 10.16, oy), xo["1"]) +cf.wire(P, (ox, P[1] - 2.54)) +pwr(cf, "+3V3", ox, P[1] - 2.54) +cap(cf, "100nF", ox - 17.78, P[1], fp=C0402, fields=C100N) +pwr(cf, "GND", ox - 17.78, P[1] + 7.62) +pwr(cf, "GND", *xo["2"]) +ro = hres(cf, "33", ox + 12.7, oy, fields=R33) +cf.wire(xo["3"], ro["1"]) +cf.pin_label(ro["2"], "CLOCK_50", length=7.62, shape="output") +cf.text("50 MHz system clock (as on the DE1). Goes to a PCLK pin, not to\n" + "B1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs only on the 45F).", 137.16, 135.89) + +cf.text("FPGA configuration", 25.4, 20.32, size=2.54, bold=True) +for i, net in enumerate(("FPGA_PROGRAMN", "FPGA_INITN", "FPGA_DONE")): + tp_pad(cf, net, 205.74 + 15.24 * i, 40.64) +cf.text("Test pads (bring-up)", 200.66, 27.94) +cf.text("Boot: master SPI (MSPI), CFG[2:0] = 010, quad SPI capable; JTAG always available (CH347).\n" + "PROG button reloads the flash, DONE LED lights when the FPGA is configured.", + 25.4, 27.94) + + +# ---------------------------------------------------------------- Ethernet sheet +ETH_SHEET_UUID = uid("sheet", "ethernet") +et = Sheet("Ethernet", uid("file", "ethernet"), f"/{ROOT_UUID}/{ETH_SHEET_UUID}", "6", paper="A3") +R22 = {"LCSC": "C25092"} +R510 = {"LCSC": "C25123"} +R2K49 = {"LCSC": "C25884"} +C22U = {"LCSC": "C45783"} + + +def vres_pull(sh, value, x, ytop, net, up, fields=None, glob=False): + """Pull resistor: up = +3V3 on top, label below; else label on top, GND below.""" + res(sh, value, x, ytop, fields=fields) + if up: + pwr(sh, "+3V3", x, ytop) + sh.wire((x, ytop + 7.62), (x, ytop + 12.7)) + sh.label(net, x, ytop + 12.7, angle=270, glob=glob) + else: + sh.wire((x, ytop), (x, ytop - 5.08)) + sh.label(net, x, ytop - 5.08, angle=90, glob=glob) + pwr(sh, "GND", x, ytop + 7.62) + + +# --- PHY +PX, PY = 190.5, 144.78 +ph = et.place("eboard", "RTL8211F-CG", ref("U"), "RTL8211F-CG", PX, PY, + ref_at=(PX + 25.4, PY - 36.83), val_at=(PX + 25.4, PY - 34.29), + fields={"LCSC": "C187932"}) +LEFT = [("20", "PHY_TXC"), ("19", "PHY_TXCTL"), ("18", "PHY_TXD0"), ("17", "PHY_TXD1"), + ("16", "PHY_TXD2"), ("15", "PHY_TXD3"), ("27", "PHY_RXC"), ("26", "PHY_RXCTL"), + ("25", "PHY_RXD0"), ("24", "PHY_RXD1"), ("23", "PHY_RXD2"), ("22", "PHY_RXD3")] +for num, name in LEFT: + et.pin_label(ph[num], name, angle=180, length=10.16, glob=False) +et.pin_label(ph["13"], "ENET_MDC", angle=180, length=10.16, shape="input") +et.pin_label(ph["14"], "ENET_MDIO", angle=180, length=10.16) +et.pin_label(ph["31"], "ENET_INT_N", angle=180, length=10.16, shape="output") +et.pin_label(ph["12"], "ENET_RST_N", angle=180, length=10.16, shape="input") +et.nc(ph["35"]) # CLKOUT unused +RIGHT = [("1", "MDI0_P"), ("2", "MDI0_N"), ("4", "MDI1_P"), ("5", "MDI1_N"), ("6", "MDI2_P"), + ("7", "MDI2_N"), ("9", "MDI3_P"), ("10", "MDI3_N"), ("32", "PHY_LED0"), + ("33", "PHY_LED1"), ("34", "PHY_LED2"), ("36", "PHY_XTAL_IN"), ("37", "PHY_XTAL_OUT"), + ("39", "PHY_RSET"), ("30", "PHY_REG_OUT")] +for num, name in RIGHT: + et.pin_label(ph[num], name, angle=0, length=10.16, glob=False) +pwr(et, "GND", *ph["41"]) +# supply pins on top: DVDD33 + DVDD_RG -> +3V3, AVDD33 -> ETH_AVDD33, DVDD10 + AVDD10 -> ETH_1V0 +d33, drg, a33, d10, a10 = ph["29"], ph["28"], ph["11"], ph["21"], ph["3"] +yj = d33[1] - 7.62 +et.wire(d33, (d33[0], yj)) +et.wire(drg, (drg[0], yj)) +et.wire((d33[0] - 10.16, yj), (d33[0], yj), (drg[0], yj)) +pwr(et, "+3V3", d33[0] - 10.16, yj) +et.wire(a33, (a33[0], yj - 7.62)) +et.label("ETH_AVDD33", a33[0], yj - 7.62, angle=90) +et.wire(d10, (d10[0], yj)) +et.wire(a10, (a10[0], yj)) +et.wire((d10[0], yj), (a10[0], yj), (a10[0] + 10.16, yj)) +et.label("ETH_1V0", a10[0] + 10.16, yj) + +# --- RGMII series resistors (22 ohm): TX close to the FPGA, RX close to the PHY +RG = [("ENET_GTX_CLK", "PHY_TXC", "input"), ("ENET_TX_EN", "PHY_TXCTL", "input"), + ("ENET_TX_DATA0", "PHY_TXD0", "input"), ("ENET_TX_DATA1", "PHY_TXD1", "input"), + ("ENET_TX_DATA2", "PHY_TXD2", "input"), ("ENET_TX_DATA3", "PHY_TXD3", "input"), + ("ENET_RX_CLK", "PHY_RXC", "output"), ("ENET_RX_DV", "PHY_RXCTL", "output"), + ("ENET_RX_DATA0", "PHY_RXD0", "output"), ("ENET_RX_DATA1", "PHY_RXD1", "output"), + ("ENET_RX_DATA2", "PHY_RXD2", "output"), ("ENET_RX_DATA3", "PHY_RXD3", "output")] +for i, (glob, loc, shape) in enumerate(RG): + y = 55.88 + 7.62 * i + (5.08 if i >= 6 else 0) + rr = hres(et, "22", 66.04, y, fields=R22) + et.pin_label(rr["1"], glob, angle=180, length=5.08, shape=shape) + et.pin_label(rr["2"], loc, angle=0, length=5.08, glob=False) +et.text("RGMII series resistors 22R:\nTX (ENET_GTX_CLK ... ENET_TX_DATA3) close to the FPGA,\n" + "RX (ENET_RX_CLK ... ENET_RX_DATA3) close to the PHY.", 30.48, 38.1) + +# --- strap resistors 4.7k (sampled at power-up / when ENET_RST_N is released) +STRAPS = [("PHY_RXD3", True, "PHYAD0 = 1"), ("PHY_RXC", False, "PHYAD1 = 0"), + ("PHY_RXCTL", False, "PHYAD2 = 0"), ("PHY_RXD2", False, "PLLOFF = 0"), + ("PHY_RXD1", True, "TXDLY = 1"), ("PHY_RXD0", True, "RXDLY = 1"), + ("PHY_LED0", True, "CFG_EXT = 1"), ("PHY_LED1", False, "CFG_LDO0 = 0"), + ("PHY_LED2", False, "CFG_LDO1 = 0")] +for i, (net, up, txt) in enumerate(STRAPS): + x = 35.56 + 15.24 * i + vres_pull(et, "4.7k", x, 205.74, net, up, fields=R4K7) + et.text(txt, x - 5.08, 231.14 if up else 228.6) +et.text("Strap resistors (RTL8211F datasheet 7.8): PHY address 1, 2 ns TXC and RXC delay inside the PHY,\n" + "RGMII I/O at 3.3 V from DVDD_RG (CFG_EXT = 1, CFG_LDO = 00), LED1/LED2 active high.", + 30.48, 182.88) + +# --- management and reset +vres_pull(et, "4.7k", 177.8, 205.74, "ENET_MDIO", True, fields=R4K7, glob=True) +vres_pull(et, "4.7k", 193.04, 205.74, "ENET_INT_N", True, fields=R4K7, glob=True) +vres_pull(et, "10k", 208.28, 205.74, "ENET_RST_N", False, fields=R10K, glob=True) +et.text("ENET_RST_N: 10k pull-down keeps the PHY in reset\nuntil the FPGA drives it high (>= 10 ms low,\n" + "wait 50 ms before MDIO access).", 172.72, 233.68) + +# --- 3.3 V and AVDD33 decoupling +y3 = 50.8 +xs = [241.3, 251.46, 261.62] +et.wire((233.68, y3), *[(x, y3) for x in xs]) +pwr(et, "+3V3", 233.68, y3) +cap_row(et, y3, xs, ["10uF", "100nF", "100nF"]) +et.text("DVDD33, DVDD_RG", 241.3, y3 - 8.89) +fb = et.place("Device", "FerriteBead", ref("FB"), "120R@100MHz", 280.67, y3, rot=90, + fp="Inductor_SMD:L_0603_1608Metric", + ref_at=(280.67, y3 - 5.08), val_at=(280.67, y3 - 2.54), centered=True, + fields={"LCSC": "C14709", "MPN": "BLM18PG121SN1D"}) +et.wire((261.62, y3), (271.78, y3), fb["1"]) +xa = [294.64, 304.8, 314.96] +et.wire(fb["2"], *[(x, y3) for x in xa], (322.58, y3), (332.74, y3)) +et.label("ETH_AVDD33", 332.74, y3) +pwr(et, "PWR_FLAG", 322.58, y3) +cap_row(et, y3, xa, ["10uF", "100nF", "100nF"]) +et.text("AVDD33 (pins 11, 40)", 294.64, y3 - 8.89) + +# --- 1.0 V from the internal switching regulator (REG_OUT -> 2.2 uH -> DVDD10/AVDD10) +y1 = 81.28 +lr = et.place("Device", "L", ref("L"), "2.2uH", 248.92, y1, rot=90, + fp="Inductor_SMD:L_0805_2012Metric", + ref_at=(248.92, y1 - 5.08), val_at=(248.92, y1 - 2.54), centered=True, + fields={"LCSC": "C394957", "MPN": "CMH201209B2R2MT"}) +et.wire((236.22, y1), lr["1"]) +et.label("PHY_REG_OUT", 236.22, y1, angle=180) +x1 = [264.16, 274.32, 284.48, 294.64, 304.8] +et.wire(lr["2"], *[(x, y1) for x in x1], (312.42, y1), (322.58, y1)) +et.label("ETH_1V0", 322.58, y1) +tp_pad(et, "ETH_1V0", 350.52, y1 - 7.62) +et.text("Test pad: PHY 1.0 V", 345.44, y1 - 20.32) +pwr(et, "PWR_FLAG", 312.42, y1) +cap_row(et, y1, x1, ["22uF", "100nF", "100nF", "100nF", "100nF"]) +et.text("1.0 V core (DVDD10 pin 21, AVDD10 pins 3, 8, 38): only for the PHY.\n" + "Inductor Isat > 600 mA, X5R/X7R capacitors.", 236.22, y1 + 15.24) + +# --- 25 MHz crystal (C9006, CL 12 pF -> 2 x 18 pF), RSET +xc, yc = 254.0, 129.54 +xt = et.place("Device", "Crystal_GND24", ref("Y"), "25MHz", xc, yc, + fp="Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm", + ref_at=(xc, yc - 10.16), val_at=(xc, yc - 7.62), centered=True, + fields={"LCSC": "C9006", "MPN": "X322525MOB4SI"}) +pwr(et, "GND", *xt["2"]) +xi, xo = xt["1"], xt["3"] +et.wire((xi[0] - 5.08, yc), xi) +et.wire(xo, (xo[0] + 5.08, yc)) +cap(et, "18pF", xi[0] - 5.08, yc, fp=C0402) +cap(et, "18pF", xo[0] + 5.08, yc, fp=C0402) +pwr(et, "GND", xi[0] - 5.08, yc + 7.62) +pwr(et, "GND", xo[0] + 5.08, yc + 7.62) +et.wire((xi[0] - 5.08, yc), (xi[0] - 5.08, yc - 7.62)) +et.label("PHY_XTAL_IN", xi[0] - 5.08, yc - 7.62, angle=90) +et.wire((xo[0] + 5.08, yc), (xo[0] + 5.08, yc - 7.62)) +et.label("PHY_XTAL_OUT", xo[0] + 5.08, yc - 7.62, angle=90) +res(et, "2.49k 1%", 287.02, 124.46, fields=R2K49) +et.wire((287.02, 124.46), (287.02, 119.38)) +et.label("PHY_RSET", 287.02, 119.38, angle=90) +pwr(et, "GND", 287.02, 132.08) + +# --- RJ45 jack with magnetics (HanRun HR911130A, symbol and footprint from KiCad library MRs) +JX, JY = 345.44, 157.48 +jk = et.place("eboard", "RJ45_Hanrun_HR911130A_Horizontal", ref("J"), "HR911130A", JX, JY, mirror=True, + fp="eboard:RJ45_Hanrun_HR911130A_Horizontal", + ref_at=(JX - 12.7, JY - 31.75), val_at=(JX - 12.7, JY - 29.21), + fields={"LCSC": "C54408"}) +for num, name in (("2", "MDI0_P"), ("3", "MDI0_N"), ("4", "MDI1_P"), ("7", "MDI1_N"), + ("5", "MDI2_P"), ("6", "MDI2_N"), ("8", "MDI3_P"), ("9", "MDI3_N"), + ("1", "MAG_CT")): + et.pin_label(jk[num], name, angle=180, length=10.16, glob=False) +for num, name in (("11", "PHY_LED2"), ("12", "LEDG_K"), ("14", "PHY_LED1"), ("13", "LEDY_K")): + et.pin_label(jk[num], name, angle=90, length=7.62, glob=False) +pwr(et, "GND", *jk["10"]) +# shield: 1M || 1 nF 2 kV to GND (keeps the 1500 V isolation with shielded cables, ESD / RF to GND) +shp = jk["SH"] +ysh = shp[1] + 2.54 +xr, xc = 325.12, 307.34 +et.wire(shp, (shp[0], ysh), (xr, ysh), (xc, ysh)) +et.label("ETH_SHIELD", shp[0], ysh, angle=180) +et.place("Device", "R", ref("R"), "1M", xr, ysh + 3.81, fp="Resistor_SMD:R_0603_1608Metric", + ref_at=(xr + 2.54, ysh + 2.54), val_at=(xr + 2.54, ysh + 5.08), fields={"LCSC": "C22935"}) +pwr(et, "GND", xr, ysh + 7.62) +et.place("Device", "C", ref("C"), "1nF 2kV", xc, ysh + 3.81, fp="Capacitor_SMD:C_1206_3216Metric", + ref_at=(xc + 2.54, ysh + 2.54), val_at=(xc + 2.54, ysh + 5.08), + fields={"LCSC": "C9196", "MPN": "FH 1206B102K202NT"}) +pwr(et, "GND", xc, ysh + 7.62) +# LEDs: active high, LED pin -> LED -> 510R -> GND; transformer centre tap: 100 nF to GND +vres_pull(et, "510", 378.46, 152.4, "LEDG_K", False, fields=R510) +vres_pull(et, "510", 391.16, 152.4, "LEDY_K", False, fields=R510) +cap(et, "100nF", 365.76, 152.4, fp=C0402, fields=C100N) +et.wire((365.76, 152.4), (365.76, 147.32)) +et.label("MAG_CT", 365.76, 147.32, angle=90) +pwr(et, "GND", 365.76, 160.02) +et.text("RJ45 with 1000Base-T magnetics. Transformer centre tap via 100 nF to GND\n" + "(voltage-mode PHY, no external MDI termination needed).\n" + "LEDs: green = LED2 (1000 Mbit/s link/activity), yellow = LED1 (100 Mbit/s).\n" + "Shield ETH_SHIELD: 1M || 1 nF 2 kV to GND, keeps the 1500 V isolation of the magnetics\n" + "with shielded cables. Layout: own copper island under the jack shell, >= 2 mm gap to GND.", + 294.64, 198.12) + +et.text("Ethernet: RTL8211F gigabit PHY, RGMII to the FPGA bank 0", 25.4, 20.32, size=2.54, bold=True) +et.text("Net names as on the DE2-115 (ENET_*), seen from the FPGA. RXC (ENET_RX_CLK) goes to a PCLK pin (A7).\n" + "3.3 V rise time must be >= 0.5 ms (TLV62569 soft start: 0.8 ms).", + 25.4, 27.94) + + +# ---------------------------------------------------------------- SDRAM sheet +SDRAM_SHEET_UUID = uid("sheet", "sdram") +sd = Sheet("SDRAM", uid("file", "sdram"), f"/{ROOT_UUID}/{SDRAM_SHEET_UUID}", "7") +SX, SY = 139.7, 101.6 +mem = sd.place("Memory_RAM", "MT48LC16M16A2TG", ref("U"), "W9825G6KH-6", SX, SY, + ref_at=(SX + 2.54, SY - 38.1), val_at=(SX + 2.54, SY - 35.56), + datasheet="https://www.winbond.com/hq/product/code-storage-flash-memory/sdram/?__locale=en&partNo=W9825G6KH", + description="256Mbit (4M x 16 x 4 banks) SDR SDRAM, 166 MHz, 3.3 V, TSOP-II-54; " + "pin compatible with MT48LC16M16A2TG", + fields={"LCSC": "C62246", "MPN": "W9825G6KH-6"}) +names = {} +for num, (px, py, pname) in lib_pins("Memory_RAM", "MT48LC16M16A2TG").items(): + names[num] = pname +DE1 = {"DQML": "DRAM_LDQM", "DQMH": "DRAM_UDQM", "~{WE}": "DRAM_WE_N", "~{CAS}": "DRAM_CAS_N", + "~{RAS}": "DRAM_RAS_N", "~{CS}": "DRAM_CS_N", "BA0": "DRAM_BA_0", "BA1": "DRAM_BA_1", + "CKE": "DRAM_CKE"} +supply = {"+3V3": set(), "GND": set()} +for num, pname in sorted(names.items(), key=lambda kv: int(kv[0])): + pt = mem[num] + if pname in ("VDD", "VDDQ"): + supply["+3V3"].add(pt) + continue + if pname in ("VSS", "VSSQ"): + supply["GND"].add(pt) + continue + if pname == "NC": + sd.nc(pt) + continue + if pname == "CLK": + sd.pin_label(pt, "SDRAM_CLK", angle=180, length=27.94, glob=False) + continue + elif pname.startswith("DQ") and pname[2:].isdigit(): + net, glob, shape = "DRAM_DQ" + pname[2:], True, "bidirectional" + elif pname.startswith("A") and pname[1:].isdigit(): + net, glob, shape = "DRAM_ADDR" + pname[1:], True, "input" + else: + net, glob, shape = DE1[pname], True, "input" + sd.pin_label(pt, net, angle=180 if pt[0] < SX else 0, length=7.62, glob=glob, shape=shape) + +# stacked supply pins (VDD + VDDQ on top, VSS + VSSQ at the bottom): one symbol each +for net, pts in supply.items(): + pts = sorted(pts) + yv = pts[0][1] + (-5.08 if net == "+3V3" else 5.08) + for pt in pts: + sd.wire(pt, (pt[0], yv)) + sd.wire(*[(pt[0], yv) for pt in pts]) + pwr(sd, net, pts[0][0], yv) + +# SDRAM clock: 22R series resistor at the FPGA (source termination) +rc = hres(sd, "22", 210.82, 139.7, fields=R22) +sd.pin_label(rc["1"], "DRAM_CLK", angle=180, length=5.08, shape="input") +sd.pin_label(rc["2"], "SDRAM_CLK", angle=0, length=5.08, glob=False) +sd.text("DRAM_CLK series resistor\nclose to the FPGA", 200.66, 127.0) + +# decoupling: 10 uF + 100 nF per VDD / VDDQ pin (pins 1, 14, 27 and 3, 9, 43, 49) +yd = 172.72 +xs = [38.1 + 12.7 * i for i in range(8)] +sd.wire((27.94, yd), *[(x, yd) for x in xs]) +pwr(sd, "+3V3", 27.94, yd) +cap_row(sd, yd, xs, ["10uF"] + ["100nF"] * 7) +sd.text("Decoupling: 10 uF bulk, 100 nF at each VDD (1, 14, 27) and VDDQ (3, 9, 43, 49) pin.", 27.94, yd - 8.89) + +sd.text("SDRAM 32 MB: Winbond W9825G6KH-6 (JLCPCB C62246), 16 bit, 166 MHz", 25.4, 20.32, + size=2.54, bold=True) +sd.text("Pin compatible with Micron MT48LC16M16A2TG (KiCad symbol, as on ULX3S). Net names as on the DE1\n" + "(DRAM_*), plus DRAM_ADDR12 for 32 MB. FPGA banks 7 + 6 (PINPLAN.md); short traces, no series\n" + "resistors on data/address (as on ULX3S).", 25.4, 27.94) + + +# ---------------------------------------------------------------- HDMI sheet +HDMI_SHEET_UUID = uid("sheet", "hdmi") +hd = Sheet("HDMI", uid("file", "hdmi"), f"/{ROOT_UUID}/{HDMI_SHEET_UUID}", "8") +HX, HY = 203.2, 104.14 +hc = hd.place("Connector", "HDMI_A", ref("J"), "HDMI_A", HX, HY, + fp="Connector_Video:HDMI_A_Amphenol_10029449-x01xLF_Horizontal", + ref_at=(HX + 12.7, HY - 22.86), val_at=(HX + 12.7, HY - 20.32), + fields={"LCSC": "C428493", "MPN": "10029449-001RLF"}) +TMDS = [("1", "D2_P"), ("3", "D2_N"), ("4", "D1_P"), ("6", "D1_N"), + ("7", "D0_P"), ("9", "D0_N"), ("10", "CLK_P"), ("12", "CLK_N")] +for num, name in TMDS: + hd.pin_label(hc[num], "TMDS_" + name, angle=180, length=10.16, glob=False) +for num in ("13", "14", "15", "16", "19"): # CEC, Utility, SCL, SDA, HPD not used + hd.nc(hc[num]) +# shields of the pairs, DDC/CEC ground and connector shell to GND +gp = sorted({hc[n] for n in ("2", "5", "8", "11", "17", "SH")}) +yg = gp[0][1] + 5.08 +for pt in gp: + hd.wire(pt, (pt[0], yg)) +hd.wire(*[(pt[0], yg) for pt in gp]) +pwr(hd, "GND", gp[0][0], yg) +# +5V for the monitor (pin 18), current limited (HDMI: max. 0.5 A) +p18 = hc["18"] +fz = hd.place("Device", "Polyfuse", ref("F"), "200mA", p18[0], p18[1] - 3.81, + fp="Fuse:Fuse_0805_2012Metric", ref_at=(p18[0] + 2.54, p18[1] - 5.08), + val_at=(p18[0] + 2.54, p18[1] - 2.54), + fields={"LCSC": "C269102", "MPN": "SMD0805B020TF"}) +pwr(hd, "+5V", *fz["1"]) +hd.wire(p18, (p18[0] - 7.62, p18[1])) +pwr(hd, "PWR_FLAG", p18[0] - 7.62, p18[1]) + +# AC coupling 22 nF per TMDS line (as on ULX3S): the sink terminates each line with +# 50 ohm to 3.3 V, the capacitor blocks the DC current of the LVCMOS33D outputs +for i, (num, name) in enumerate(TMDS): + y = 63.5 + 10.16 * i + cc = hd.place("Device", "C", ref("C"), "22nF", 101.6, y, rot=90, fp=C0402, + ref_at=(101.6, y - 6.35), val_at=(101.6, y - 3.81), centered=True, + fields={"LCSC": "C1532"}) + hd.pin_label(cc["1"], "HDMI_" + name, angle=180, length=7.62, shape="output") + hd.pin_label(cc["2"], "TMDS_" + name, angle=0, length=7.62, glob=False) + +# ESD protection on the connector side of the coupling capacitors (flow-through, 0.3 pF) +tl = ["TMDS_" + n for _, n in TMDS] +for k, ex in ((0, 96.52), (4, 165.1)): + ey = 154.94 + e4 = hd.place("Power_Protection", "TPD4E05U06DQA", ref("U"), "TPD4E05U06", ex, ey, + ref_at=(ex - 2.54, ey - 11.43), val_at=(ex - 2.54, ey - 8.89), + fields={"LCSC": "C2827646"}) + for num, net in zip(("1", "2", "4", "5"), tl[k:k + 4]): + hd.pin_label(e4[num], net, angle=180 if num in ("1", "2") else 0, length=5.08, glob=False) + for num in ("6", "7", "9", "10"): + hd.nc(e4[num]) + pwr(hd, "GND", *e4["3"]) +hd.text("ESD protection TPD4E05U06 (0.3 pF), at the connector,\n" + "between connector and coupling capacitors", 25.4, 172.72) + +hd.text("HDMI output (type A), TMDS driven directly by the FPGA", 25.4, 20.32, size=2.54, bold=True) +hd.text("FPGA bank 0, each pair on an A/B ball pair, IO_TYPE=LVCMOS33D (as ULX3S GPDI). 640x480 and 720p work\n" + "with the ECP5 serializers (ODDRX1F/ODDRX2F). Route the pairs as 100 ohm differential, equal length.\n" + "Not connected (FPGA pin budget): DDC (SCL/SDA, no EDID), HPD, CEC, Utility.\n" + "ESD: two TPD4E05U06 on the TMDS lines at the connector (users plug HDMI cables in and out).", + 25.4, 27.94) +hd.text("AC coupling capacitors 22 nF,\nclose to the connector", 88.9, 50.8) +hd.text("+5V for the monitor, PTC 200 mA", HX + 5.08, HY - 45.72) + + +# ---------------------------------------------------------------- user I/O sheet (DE1 names) +UIO_SHEET_UUID = uid("sheet", "user_io") +ui = Sheet("User IO", uid("file", "user_io"), f"/{ROOT_UUID}/{UIO_SHEET_UUID}", "9", paper="A3") +R330 = {"LCSC": "C25104"} +R470 = {"LCSC": "C25117"} +R47K = {"LCSC": "C25792"} +LED_RED = {"LCSC": "C2286", "MPN": "KT-0603R"} +LED_YG = {"LCSC": "C965805", "MPN": "XL-1608SYGC-06"} +HC14 = ("74xx", "74HC14") +HC14_REF = ref("U") +HC14_F = {"LCSC": "C5605", "MPN": "74HC14D"} +HC14_FP = "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" + +# --- KEY[3:0]: push button, RC, Schmitt trigger inverter -> active low, debounced (as on the DE1) +GATES = [(1, "KEY0"), (2, "KEY1"), (3, "KEY2"), (4, "KEY3")] +for i, (unit, name) in enumerate(GATES): + y = 55.88 + 22.86 * i + pwr(ui, "+3V3", 35.56, y) + sw = ui.place("Switch", "SW_Push", ref("SW"), "TS-1187A", 45.72, y, + fp="Button_Switch_SMD:SW_Push_1P1T_XKB_TS-1187A", + ref_at=(45.72, y - 5.08), val_at=(45.72, y - 2.54), centered=True, + fields={"LCSC": "C318884", "MPN": "XKB TS-1187A-B-A-B"}) + ui.wire((35.56, y), sw["1"]) + rr = hres(ui, "1k", 58.42, y, fields=R1K) + ui.wire(sw["2"], rr["1"]) + g = ui.place(*HC14, HC14_REF, "74HC14D", 100.33, y, unit=unit, fp=HC14_FP, + ref_at=(100.33, y - 5.08), val_at=(100.33, y - 7.62), centered=True, fields=HC14_F) + gin, gout = sorted(set(g.values())) + ui.wire(rr["2"], (69.85, y), (80.01, y), gin) + cap(ui, "100nF", 69.85, y, fp=C0402, fields=C100N) + pwr(ui, "GND", 69.85, y + 7.62) + res(ui, "47k", 80.01, y, fields=R47K) + pwr(ui, "GND", 80.01, y + 7.62) + ui.pin_label(gout, name, length=7.62, shape="output") +for unit, y in ((5, 152.4), (6, 167.64)): # unused gates: input to GND + g = ui.place(*HC14, HC14_REF, "74HC14D", 100.33, y, unit=unit, fp=HC14_FP, + ref_at=(100.33, y - 5.08), val_at=(100.33, y - 7.62), centered=True, fields=HC14_F) + gin, gout = sorted(set(g.values())) + ui.wire(gin, (gin[0] - 5.08, gin[1])) + pwr(ui, "GND", gin[0] - 5.08, gin[1]) + ui.nc(gout) +pu = ui.place(*HC14, HC14_REF, "74HC14D", 60.96, 162.56, unit=7, fp=HC14_FP, + ref_at=(63.5, 152.4), val_at=(63.5, 154.94), fields=HC14_F) +pwr(ui, "+3V3", *pu["14"]) +pwr(ui, "GND", *pu["7"]) +cap(ui, "100nF", 43.18, 154.94, fp=C0402, fields=C100N) +pwr(ui, "+3V3", 43.18, 154.94) +pwr(ui, "GND", 43.18, 162.56) +ui.text("KEY[3:0]: high when not pressed, low when pressed (as on the DE1).\n" + "Debounced: button charges 100 nF via 1k, 47k discharges it (~5 ms),\n" + "74HC14 Schmitt trigger inverts. Usable as clock input in lab designs.", 30.48, 38.1) + +# --- LEDR[9:0] (red) and LEDG[5:0] (yellow-green): active high, FPGA pin -> R -> LED -> GND +LEDS = [(f"LEDR{i}", "red", "1k", R1K, LED_RED) for i in range(10)] + \ + [(f"LEDG{i}", "green", "470", R470, LED_YG) for i in range(6)] +for i, (name, colour, rv, rf, lf) in enumerate(LEDS): + y = 50.8 + 7.62 * i + (5.08 if i >= 10 else 0) + rl = hres(ui, rv, 172.72, y, fields=rf) + ui.pin_label(rl["1"], name, angle=180, length=5.08, shape="input") + led = ui.place("Device", "LED", ref("D"), colour, 186.69, y, rot=180, fp=LED0603, + ref_at=(186.69, y - 5.08), val_at=(186.69, y - 2.54), centered=True, fields=lf) + ui.wire(rl["2"], led["2"]) + ui.wire(led["1"], (195.58, y)) + pwr(ui, "GND", 195.58, y) +ui.text("LEDR[9:0], LEDG[5:0]: active high (as on the DE1).\n" + "Red KT-0603R 1k (~1.3 mA), yellow-green XL-1608SYGC 470R (~2.3 mA).", 154.94, 38.1) + +# --- HEX0 ... HEX3: 7-segment displays, common anode, segments active low (as on the DE1) +SEGS = "ABCDEFG" +for d, (bx, by) in enumerate(((335.28, 132.08), (256.54, 132.08), (335.28, 50.8), (256.54, 50.8))): + for k, seg in enumerate(SEGS): + y = by + 7.62 * k + rs = hres(ui, "330", bx + 12.7, y, fields=R330) + ui.pin_label(rs["1"], f"HEX{d}_{k}", angle=180, length=5.08, shape="input") + ui.pin_label(rs["2"], f"H{d}_{seg}", angle=0, length=5.08, glob=False) + lp = lib_pins("eboard", "SM410561N") + ax = lp["7"][0] # x of the segment pins in the symbol + dx = bx + 48.26 - ax + dy = by + 30.48 + disp = ui.place("eboard", "SM410561N", ref("U"), "SM410561N", dx, dy, + ref_at=(dx - 15.24, dy - 22.86), val_at=(dx - 15.24, dy - 20.32), + fields={"LCSC": "C141368"}) + for num, seg in (("7", "A"), ("6", "B"), ("4", "C"), ("2", "D"), ("1", "E"), ("9", "F"), ("10", "G")): + ui.pin_label(disp[num], f"H{d}_{seg}", angle=180, length=7.62, glob=False) + ui.nc(disp["5"]) # DP not used (as on the DE1) + ca = sorted({disp["3"], disp["8"]}) + yc = ca[0][1] - 5.08 + for pt in ca: + ui.wire(pt, (pt[0], yc)) + ui.wire(*[(pt[0], yc) for pt in ca]) + pwr(ui, "+3V3", ca[0][0], yc) + ui.text(f"HEX{d}", bx + 30.48, by - 7.62, size=2.54, bold=True) +ui.text("HEX0[6:0] ... HEX3[6:0]: segment 0 = a ... 6 = g, active low (as on the DE1).\n" + "Common anode on 3.3 V, 330R per segment (~4 mA). Decimal point not connected.", + 256.54, 38.1) + +# --- SW[9:0]: slide switches, common contact via 1k to the FPGA +ys = 218.44 +for i in range(10): + x = 45.72 + 35.56 * i + ss = ui.place("Switch", "SW_SPDT", ref("SW"), "SS-12D07-5", x, ys, + fp="Button_Switch_THT:SW_Slide_SPDT_Straight_CK_OS102011MS2Q", + ref_at=(x - 2.54, ys + 7.62), val_at=(x - 2.54, ys + 10.16), + fields={"LCSC": "C2857673", "MPN": "ROCPU SS-12D07-5", + "Alternative": "C&K OS102011MS2QN1 (C221829), same footprint"}) + rw = hres(ui, "1k", x - 10.16, ys, fields=R1K) + ui.wire(ss["2"], rw["2"]) + ui.pin_label(rw["1"], f"SW{i}", angle=180, length=5.08, shape="input") + ui.wire(ss["1"], (x + 7.62, ss["1"][1])) + pwr(ui, "+3V3", x + 7.62, ss["1"][1]) + ui.wire(ss["3"], (x + 7.62, ss["3"][1])) + pwr(ui, "GND", x + 7.62, ss["3"][1]) +ui.text("SW[9:0]: vertical slide switches ROCPU SS-12D07-5 (C&K OS102011 footprint; C&K OS102011MS2QN1 fits too),\n" + "through hole, not debounced (as on the DE1).\n" + "1k series resistor protects the FPGA pin if it is driven as an output by mistake.", 30.48, 198.12) + +ui.text("User I/O (DE1 compatible): SW, KEY, LEDR, LEDG, HEX", 25.4, 20.32, size=2.54, bold=True) +ui.text("Net names = DE1 port names, see kicad/README.md. FPGA banks 3, 6 and 8 (PINPLAN.md).", 25.4, 27.94) + + +# ---------------------------------------------------------------- GPIO headers, Pmods, ESD +GPIO_SHEET_UUID = uid("sheet", "gpio") +gp = Sheet("GPIO", uid("file", "gpio"), f"/{ROOT_UUID}/{GPIO_SHEET_UUID}", "10", paper="A3") + + +def de1_index(pin): + """DE1 GPIO header pin -> GPIO index, or None for supply pins.""" + if pin <= 10: + return pin - 1 + if 13 <= pin <= 28: + return pin - 3 + if 31 <= pin <= 40: + return pin - 5 + return None + + +def supply_pin(sh, pt, net, left): + """Supply pin of a connector: long wire past the labels, then the power symbol.""" + x2 = pt[0] - 25.4 if left else pt[0] + 25.4 + sh.wire(pt, (x2, pt[1])) + pwr(sh, net, x2, pt[1]) + + +ADA = {37: "ADA_POWER_ON", 38: "ADA_OEB", 40: "ADA_OEA"} # GPIO_0 pins fixed for the THDB-ADA +for hdr, (hx, hy), ref_name in (("GPIO_0", (76.2, 81.28), "JP1"), ("GPIO_1", (190.5, 81.28), "JP2")): + j = gp.place("Connector_Generic", "Conn_02x20_Odd_Even", ref("J"), f"{hdr} ({ref_name})", hx, hy, + fp="Connector_IDC:IDC-Header_2x20_P2.54mm_Vertical", + ref_at=(hx - 2.54, hy - 27.94), val_at=(hx - 2.54, hy - 30.48), + fields={"LCSC": "C5200276", "MPN": "EH254V-12-40P"}) + for pin in range(1, 41): + pt = j[str(pin)] + left = pin % 2 == 1 + if pin in (11, 29): # DE1: 11 = 5 V, 29 = 3.3 V; eboard: both 3.3 V + supply_pin(gp, pt, "+3V3", left) + elif pin in (12, 30): + supply_pin(gp, pt, "GND", left) + elif hdr == "GPIO_0" and pin in ADA: + gp.pin_label(pt, ADA[pin], angle=180 if left else 0, length=25.4, glob=False) + elif hdr == "GPIO_0" and pin == 39: + gp.nc(pt) + else: + gp.pin_label(pt, f"{hdr}_{de1_index(pin)}", angle=180 if left else 0, length=7.62) + +# THDB-ADA control pins on GPIO_0 (see PINPLAN.md): fixed levels instead of FPGA pins +for k, (net, up, txt) in enumerate((("ADA_POWER_ON", True, "pin 37 POWER_ON = 1"), + ("ADA_OEB", False, "pin 38 ADC_OEB = 0"), + ("ADA_OEA", False, "pin 40 ADC_OEA = 0"))): + x = 347.98 + 20.32 * k + vres_pull(gp, "10k", x, 66.04, net, up, fields=R10K) + gp.text(txt, x - 6.35, 96.52 + 2.54 * k) +gp.text("THDB-ADA: GPIO_0 pins 37-40 are not FPGA pins.\nPOWER_ON pull-up (ADC and clock buffer on),\n" + "OEA/OEB pull-down (ADC outputs enabled), pin 39 unused.", 340.36, 43.18) + +# Pmod A / B (Digilent Pmod interface, 12 pin, right angle female): pin k (1-6, upper row) = pad 2k-1, +# pin k (7-12, lower row) = pad 2(k-6); pins 5/11 GND, 6/12 3.3 V +for name, (px, py), base in (("Pmod A", (292.1, 63.5), 0), ("Pmod B", (292.1, 101.6), 8)): + pm = gp.place("Connector_Generic", "Conn_02x06_Odd_Even", ref("J"), name, px, py, + fp="Connector_PinSocket_2.54mm:PinSocket_2x06_P2.54mm_Horizontal", + ref_at=(px - 2.54, py - 12.7), val_at=(px - 2.54, py - 15.24), + fields={"LCSC": "C5333437", "MPN": "A2541HWR-2x6P"}) + for pmod_pin in range(1, 13): + pad = 2 * pmod_pin - 1 if pmod_pin <= 6 else 2 * (pmod_pin - 6) + pt = pm[str(pad)] + left = pad % 2 == 1 + if pmod_pin in (5, 11): + supply_pin(gp, pt, "GND", left) + elif pmod_pin in (6, 12): + supply_pin(gp, pt, "+3V3", left) + else: + io = pmod_pin - 1 if pmod_pin <= 4 else pmod_pin - 3 + gp.pin_label(pt, f"GPIO_0_{base + io}", angle=180 if left else 0, length=7.62) +gp.text("Pmod A = GPIO_0_0..7, Pmod B = GPIO_0_8..15 (shared with GPIO_0:\n" + "use either a Pmod or a card on GPIO_0). Pmod pin 1-4 / 7-10 = IO 1-8.\n" + "Check pin 1 orientation against the Digilent Pmod specification in layout.", 248.92, 27.94) + +# ESD protection: TPD4E05U06 (4 lines, 0.3 pF, flow-through) on all 68 FPGA lines +lines = [f"GPIO_0_{i}" for i in range(32)] + [f"GPIO_1_{i}" for i in range(36)] +for k in range(0, len(lines), 4): + n = k // 4 + ex, ey = 45.72 + 76.2 * (n % 5), 142.24 + 30.48 * (n // 5) + e4 = gp.place("Power_Protection", "TPD4E05U06DQA", ref("U"), "TPD4E05U06", ex, ey, + ref_at=(ex - 2.54, ey - 11.43), val_at=(ex - 2.54, ey - 8.89), + fields={"LCSC": "C2827646", "MPN": "TPD4E05U06DQAR"}) + for num, net in zip(("1", "2", "4", "5"), lines[k:k + 4]): + gp.pin_label(e4[num], net, angle=180 if num in ("1", "2") else 0, length=5.08) + for num in ("6", "7", "9", "10"): + gp.nc(e4[num]) + pwr(gp, "GND", *e4["3"]) + +gp.text("GPIO expansion headers (DE1 compatible), Pmod A/B, ESD protection", 25.4, 20.32, + size=2.54, bold=True) +gp.text("2x20 box headers at the DE1 positions (JP1 pin 1 at (125.603, 118.745) mm, JP2 20.32 mm to the right,\n" + "see PINPLAN.md). DE1 pinout: pins 1-10 = GPIO_x[0..9], 13-28 = [10..25], 31-40 = [26..35],\n" + "12/30 = GND. Pin 29 = 3.3 V; pin 11 = 3.3 V instead of 5 V on the DE1: no 5 V on the headers.\n" + "FPGA pins connected directly (as on ULX3S), ESD arrays close to the header pins.", 25.4, 27.94) +for i, where in enumerate(("GPIO headers", "Pmods")): + lx = 355.6 + 25.4 * i + gp.place("Connector", "TestPoint", ref("TP"), "GND", lx, 114.3, fp=TP_LOOP, + ref_at=(lx + 2.54, 110.49), val_at=(lx + 2.54, 113.03), + fields={"LCSC": "C238127", "MPN": "Keystone 5011"}) + gp.wire((lx, 114.3), (lx, 116.84)) + pwr(gp, "GND", lx, 116.84) +gp.text("Scope ground loops (Keystone 5011, black) for the\n" + "crocodile clips: one at the GPIO headers, one at the Pmods.", 345.44, 104.14) +gp.text("ESD protection TPD4E05U06 (DFN 2.5x1 mm, flow-through), one per 4 lines, placed at the headers", 25.4, 119.38) + + +# ---------------------------------------------------------------- FPGA bank sheets +# Ball assignment (preliminary, PINPLAN.md): swap within a bank during layout. +BALLS = {} +# bank 0: Ethernet RGMII (RXC on PCLKT0_0 = A7) + HDMI (A/B pairs, A = P) +BALLS.update({ + "HDMI_D2_P": "A2", "HDMI_D2_N": "B3", "HDMI_D1_P": "A3", "HDMI_D1_N": "A4", + "HDMI_D0_P": "C4", "HDMI_D0_N": "B4", "HDMI_CLK_P": "A5", "HDMI_CLK_N": "A6", + "ENET_RX_CLK": "A7", "ENET_RX_DV": "A8", "ENET_RX_DATA0": "B7", "ENET_RX_DATA1": "C7", + "ENET_RX_DATA2": "B6", "ENET_RX_DATA3": "C6", + "ENET_GTX_CLK": "D7", "ENET_TX_EN": "E7", "ENET_TX_DATA0": "D6", "ENET_TX_DATA1": "E6", + "ENET_TX_DATA2": "D5", "ENET_TX_DATA3": "E5", + "ENET_MDC": "D4", "ENET_MDIO": "E4", "ENET_RST_N": "B5", "ENET_INT_N": "C5"}) +# bank 1: GPIO_0[31:0], [0] = C8 (PCLKT1_0), [2] = E8 (PCLKT1_1); (true, complement) pairs +b1 = [("C8", "B8"), ("E8", "D8"), ("B9", "C9"), ("D9", "E9"), ("A9", "A10"), ("B10", "C10"), + ("D10", "E10"), ("B11", "C11"), ("D11", "E11"), ("A11", "A12"), ("B12", "C12"), + ("D12", "E12"), ("B13", "C13"), ("D13", "E13"), ("A13", "A14"), ("B14", "A15")] +# bank 2: GPIO_1[31:0], [0] = K16 (PCLKT2_0), [2] = J16 (PCLKT2_1) +b2 = [("K16", "K15"), ("J16", "J15"), ("J14", "K14"), ("G16", "H15"), ("J13", "J12"), + ("H12", "H13"), ("G14", "H14"), ("F16", "G15"), ("F15", "E16"), ("G12", "G13"), + ("F13", "F12"), ("D16", "E15"), ("E14", "F14"), ("C16", "C15"), ("C14", "D14"), + ("B16", "B15")] +for i, (t, c) in enumerate(b1): + BALLS[f"GPIO_0_{2 * i}"], BALLS[f"GPIO_0_{2 * i + 1}"] = t, c +for i, (t, c) in enumerate(b2): + BALLS[f"GPIO_1_{2 * i}"], BALLS[f"GPIO_1_{2 * i + 1}"] = t, c +# bank 3: GPIO_1[35:32] (2 pairs next to bank 2), UART, HEX0-HEX2, HEX3[4:0] +BALLS.update({"GPIO_1_32": "L16", "GPIO_1_33": "L15", "GPIO_1_34": "M16", "GPIO_1_35": "M15", + "UART_TXD": "K12", "UART_RXD": "K13"}) +b3 = ["L13", "L12", "L14", "M14", "N16", "P15", "M13", "N14", "P16", "R16", "N13", "T15", + "R15", "P14", "P13", "T14", "R13", "R14", "M12", "N12", "R12", "T13", "M11", "P12", + "N11", "P11"] +hex_ = [f"HEX{d}_{s}" for d in range(4) for s in range(7)] +for n, b in zip(hex_[:26], b3): + BALLS[n] = b +# bank 6: CLOCK_50 on M1 (PCLKT6_0), SDRAM control next to bank 7, SW, KEY, LEDR +BALLS["CLOCK_50"] = "M1" +for n, b in zip(["DRAM_BA_0", "DRAM_BA_1", "DRAM_CS_N", "DRAM_RAS_N", "DRAM_CAS_N", "DRAM_WE_N", + "DRAM_CKE"], ["K4", "K5", "L4", "L5", "L1", "L2", "M2"]): + BALLS[n] = b +b6 = ["L3", "M3", "N1", "P2", "M4", "P1", "R1", "N3", "N4", "R2", "P3", "T2", "P4", "R4", + "R3", "T3", "R5", "M5", "T4", "N5", "M6", "N6", "P6", "P5"] +for n, b in zip([f"LEDR{i}" for i in range(10)] + [f"SW{i}" for i in range(10)] + + [f"KEY{i}" for i in range(4)], b6): + BALLS[n] = b +# bank 7: SDRAM DQ, DQM, CLK, ADDR +b7 = ["B1", "B2", "C3", "D3", "C1", "E3", "C2", "F3", "D1", "F4", "E2", "F5", "G5", "F2", + "G4", "E1", "F1", "G3", "G2", "H3", "H5", "J4", "H4", "J5", "G1", "J3", "H2", "K3", + "J1", "K1", "J2", "K2"] +for n, b in zip([f"DRAM_DQ{i}" for i in range(8)] + ["DRAM_LDQM"] + + [f"DRAM_DQ{i}" for i in range(8, 16)] + ["DRAM_UDQM", "DRAM_CLK"] + + [f"DRAM_ADDR{i}" for i in range(13)], b7): + BALLS[n] = b +# bank 8 (free pins after the SPI flash): LEDG, HEX3[6:5] +B8_BALLS = {"LEDG0": "T6", "LEDG1": "R7", "LEDG2": "R6", "LEDG3": "P7", "LEDG4": "R8", + "LEDG5": "P8", "HEX3_5": "M8", "HEX3_6": "M9"} +BALLS.update(B8_BALLS) +assert len(BALLS) == 192 and len(set(BALLS.values())) == 192, (len(BALLS), len(set(BALLS.values()))) +BALL_NET = {b: n for n, b in BALLS.items()} + + +def fpga_dir(n): + """Global label shape, seen from the FPGA.""" + if n.startswith(("GPIO_", "DRAM_DQ")) or n == "ENET_MDIO": + return "bidirectional" + if n.startswith(("SW", "KEY", "ENET_RX", "CLOCK_50", "UART_RXD", "ENET_INT")): + return "input" + return "output" + + +BANK_UNIT = {0: 1, 1: 2, 2: 3, 3: 4, 6: 5, 7: 6} + + +def bank_unit(sh, bank, x, y, note): + u = sh.place(*FPGA, FPGA_REF, "LFE5U-25F-7BG256I", x, y, unit=BANK_UNIT[bank], + ref_at=(x - 30.48, y - 45.72), val_at=(x - 30.48, y - 43.18)) + pins = lib_pins(*FPGA, BANK_UNIT[bank]) + for num, (px, py, name) in pins.items(): + if name.startswith("VCCIO"): + continue + net = BALL_NET[num] + sh.pin_label(u[num], net, angle=180 if px < 0 else 0, length=2.54, shape=fpga_dir(net)) + for num, (px, py, name) in pins.items(): + if name.startswith("VCCIO"): + pwr(sh, "+3V3", *u[num]) + break + sh.text(note, x - 30.48, y + 33.02) + + +fb = [] +for key, title, banks, notes in ( + ("fpga_banks_01", "FPGA banks 0 1", (0, 1), + ("Bank 0 (top left): Ethernet RGMII, ENET_RX_CLK on PCLKT0_0 (A7);\n" + "HDMI pairs LVCMOS33D on A/B ball pairs (A = P).", + "Bank 1 (top right): GPIO_0[31:0] incl. Pmod A/B.\n" + "GPIO_0[0] / [2] on PCLKT1_0 C8 / PCLKT1_1 E8; GPIO_0[2k] / [2k+1]\n" + "on the true / complement ball of a pair (header neighbours).")), + ("fpga_banks_23", "FPGA banks 2 3", (2, 3), + ("Bank 2 (right upper): GPIO_1[31:0].\n" + "GPIO_1[0] / [2] on PCLKT2_0 K16 / PCLKT2_1 J16; GPIO_1[2k] / [2k+1]\n" + "on true LVDS pairs (A/B, C/D).", + "Bank 3 (right lower): GPIO_1[35:32] (pairs PR26),\n" + "UART_TXD / UART_RXD, HEX0-HEX2, HEX3[4:0].")), + ("fpga_banks_67", "FPGA banks 6 7", (6, 7), + ("Bank 6 (left lower): CLOCK_50 on PCLKT6_0 (M1),\n" + "SDRAM BA/CS/RAS/CAS/WE/CKE, LEDR, SW, KEY.", + "Bank 7 (left upper): SDRAM DQ[15:0], LDQM/UDQM, CLK, ADDR[12:0]."))): + sid = uid("sheet", key) + sh = Sheet(title, uid("file", key), f"/{ROOT_UUID}/{sid}", str(11 + len(fb))) + bank_unit(sh, banks[0], 78.74, 101.6, notes[0]) + bank_unit(sh, banks[1], 213.36, 101.6, notes[1]) + sh.text(title.replace("FPGA banks", "FPGA banks").replace(" 0 1", " 0 and 1") + .replace(" 2 3", " 2 and 3").replace(" 6 7", " 6 and 7"), 25.4, 20.32, size=2.54, bold=True) + sh.text("All banks VCCIO = 3.3 V. Ball assignment preliminary (PINPLAN.md): pins may be\n" + "swapped within a bank during layout; the LPF follows the schematic.\n" + "Balls B1 B2 A2 B3 B14 A15 B15 B16 (PLL inputs on the 45F) carry no clocks.", + 25.4, 27.94) + fb.append((sid, title, key, sh)) + + +# ---------------------------------------------------------------- test points sheet +TP_SHEET_UUID = uid("sheet", "testpoints") +tps = Sheet("Test points", uid("file", "testpoints"), f"/{ROOT_UUID}/{TP_SHEET_UUID}", "14") +tps.text("Test points and mounting holes", 25.4, 20.32, size=2.54, bold=True) +tps.text("Round top-layer pads (1.5 mm, TestPoint_Pad_D1.5mm) for probes and test needles. No part:\n" + "not in the BOM, not in the placement file. Further test pads on their sheets: VBUS (USB),\n" + "FPGA_PROGRAMN / FPGA_INITN / FPGA_DONE (FPGA config), ETH_1V0 (Ethernet).\n" + "JTAG: the 1x6 header footprint J2 (USB sheet, not fitted) serves as test access.\n" + "Scope ground loops for the lab (Keystone 5011): GPIO sheet.", 25.4, 27.94) +tps.text("Supply rails", 25.4, 55.88, bold=True) +for i, net in enumerate(("+5V", "+3V3", "+2V5", "+1V1")): + tp_pad(tps, net, 38.1 + 25.4 * i, 71.12, kind="rail") +tps.text("GND, spread over the board (next to the rail pads, FPGA, Ethernet, GPIO)", 25.4, 93.98, bold=True) +for i in range(4): + tp_pad(tps, "GND", 38.1 + 25.4 * i, 109.22, kind="gnd") +tps.text("Signals", 25.4, 132.08, bold=True) +for i, net in enumerate(("CLOCK_50", "UART_TXD", "UART_RXD")): + tp_pad(tps, net, 38.1 + 25.4 * i, 147.32, glob=True) + +# mounting holes at the DE1 positions (PINPLAN.md), plated, connected to GND +tps.text("Mounting holes (M3, DE1 positions)", 152.4, 55.88, bold=True) +MH = [(4.191, 4.191), (4.191, 32.385), (4.191, 147.955), + (147.955, 4.191), (147.955, 32.385), (147.955, 147.955)] +for i, (bx, by) in enumerate(MH): + hx, hy = 160.02 + 20.32 * (i % 3), 71.12 + 27.94 * (i // 3) + h = tps.place("Mechanical", "MountingHole_Pad", ref("H"), "M3", hx, hy, + fp="MountingHole:MountingHole_3.2mm_M3_Pad_Via", in_bom=False, + ref_at=(hx + 3.81, hy - 2.54), val_at=(hx + 3.81, hy)) + tps.wire(h["1"], (h["1"][0], h["1"][1] + 2.54)) + pwr(tps, "GND", h["1"][0], h["1"][1] + 2.54) + tps.text(f"({bx:g}, {by:g})", hx - 5.08, hy + 12.7) +tps.text("Board coordinates in mm, origin bottom left, y up (DE1 outline).\n" + "Plated M3 holes with via ring, connected to GND: the metal\n" + "standoffs ground the board to the lab bench / case.", 152.4, 129.54) + + +# ---------------------------------------------------------------- root sheet +root = Sheet("Top", ROOT_UUID, f"/{ROOT_UUID}", "1") + + +def sheet_block(sid, name, fname, x, y, page): + return f"""\t(sheet +\t\t(at {r(x)} {r(y)}) +\t\t(size 38.1 20.32) +\t\t(exclude_from_sim no) +\t\t(in_bom yes) +\t\t(on_board yes) +\t\t(dnp no) +\t\t(stroke +\t\t\t(width 0.1524) +\t\t\t(type solid) +\t\t) +\t\t(fill +\t\t\t(color 0 0 0 0.0000) +\t\t) +\t\t(uuid "{sid}") +\t\t(property "Sheetname" "{name}" +\t\t\t(at {r(x)} {r(y - 0.7116)} 0) +\t\t\t(effects +\t\t\t\t(font +\t\t\t\t\t(size 1.27 1.27) +\t\t\t\t) +\t\t\t\t(justify left bottom) +\t\t\t) +\t\t) +\t\t(property "Sheetfile" "{fname}" +\t\t\t(at {r(x)} {r(y + 20.9046)} 0) +\t\t\t(effects +\t\t\t\t(font +\t\t\t\t\t(size 1.27 1.27) +\t\t\t\t) +\t\t\t\t(justify left top) +\t\t\t) +\t\t) +\t\t(instances +\t\t\t(project "{PROJECT}" +\t\t\t\t(path "/{ROOT_UUID}" +\t\t\t\t\t(page "{page}") +\t\t\t\t) +\t\t\t) +\t\t) +\t) +""" + + +blocks = (sheet_block(POWER_SHEET_UUID, "Power", "power.kicad_sch", 50.8, 50.8, "2") + + sheet_block(USB_SHEET_UUID, "USB", "usb.kicad_sch", 101.6, 50.8, "3") + + sheet_block(FPWR_SHEET_UUID, "FPGA power", "fpga_power.kicad_sch", 152.4, 50.8, "4") + + sheet_block(FCFG_SHEET_UUID, "FPGA config", "fpga_config.kicad_sch", 203.2, 50.8, "5") + + sheet_block(ETH_SHEET_UUID, "Ethernet", "ethernet.kicad_sch", 50.8, 88.9, "6") + + sheet_block(SDRAM_SHEET_UUID, "SDRAM", "sdram.kicad_sch", 101.6, 88.9, "7") + + sheet_block(HDMI_SHEET_UUID, "HDMI", "hdmi.kicad_sch", 152.4, 88.9, "8") + + sheet_block(UIO_SHEET_UUID, "User IO", "user_io.kicad_sch", 203.2, 88.9, "9") + + sheet_block(GPIO_SHEET_UUID, "GPIO", "gpio.kicad_sch", 50.8, 127.0, "10") + + "".join(sheet_block(sid, t, k + ".kicad_sch", 101.6 + 50.8 * i, 127.0, str(11 + i)) + for i, (sid, t, k, _) in enumerate(fb)) + + sheet_block(TP_SHEET_UUID, "Test points", "testpoints.kicad_sch", 101.6, 165.1, "14")) +root.text("eboard - ECP5 SoC board with GbE Ethernet", 25.4, 20.32, size=2.54, bold=True) +root.text("Supply rails are global power symbols (+5V, +3V3, +2V5, +1V1, GND).\n" + "Signals between sheets are global labels, as on ULX3S.", 25.4, 30.48) + +os.makedirs(OUT, exist_ok=True) +open(f"{OUT}/power.kicad_sch", "w").write(pw.render("eboard - Power")) +open(f"{OUT}/usb.kicad_sch", "w").write(us.render("eboard - USB")) +open(f"{OUT}/fpga_power.kicad_sch", "w").write(fpw.render("eboard - FPGA power")) +open(f"{OUT}/fpga_config.kicad_sch", "w").write(cf.render("eboard - FPGA config")) +open(f"{OUT}/ethernet.kicad_sch", "w").write(et.render("eboard - Ethernet")) +open(f"{OUT}/sdram.kicad_sch", "w").write(sd.render("eboard - SDRAM")) +open(f"{OUT}/hdmi.kicad_sch", "w").write(hd.render("eboard - HDMI")) +open(f"{OUT}/user_io.kicad_sch", "w").write(ui.render("eboard - User IO")) +open(f"{OUT}/gpio.kicad_sch", "w").write(gp.render("eboard - GPIO")) +open(f"{OUT}/testpoints.kicad_sch", "w").write(tps.render("eboard - Test points")) +for sid, t, k, sh in fb: + open(f"{OUT}/{k}.kicad_sch", "w").write(sh.render("eboard - " + t)) +open(f"{OUT}/{PROJECT}.kicad_sch", "w").write(root.render("eboard", extra=blocks)) + +pro_path = f"{OUT}/{PROJECT}.kicad_pro" +pro = json.load(open(pro_path)) if os.path.exists(pro_path) else { + "meta": {"filename": f"{PROJECT}.kicad_pro", "version": 3}, "text_variables": {}} +pro["sheets"] = [[ROOT_UUID, "Root"], [POWER_SHEET_UUID, "Power"], [USB_SHEET_UUID, "USB"], + [FPWR_SHEET_UUID, "FPGA power"], [FCFG_SHEET_UUID, "FPGA config"], + [ETH_SHEET_UUID, "Ethernet"], [SDRAM_SHEET_UUID, "SDRAM"], + [HDMI_SHEET_UUID, "HDMI"], [UIO_SHEET_UUID, "User IO"], + [GPIO_SHEET_UUID, "GPIO"]] + [[sid, t] for sid, t, k, _ in fb] + [[TP_SHEET_UUID, "Test points"]] +json.dump(pro, open(pro_path, "w"), indent=2) +print("ok") diff --git a/kicad/usb.kicad_sch b/kicad/usb.kicad_sch new file mode 100644 index 0000000..fd2dc77 --- /dev/null +++ b/kicad/usb.kicad_sch @@ -0,0 +1,8189 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "d4074a26-fe99-5530-a468-3f176d79f152") + (paper "A4") + (title_block + (title "eboard - USB") + (date "2026-11-08") + (rev "0.1") + (comment 1 "CERN-OHL-S-2.0") + ) + (lib_symbols +(symbol "Connector:TestPoint" +(property "Reference" "TP" + (at 0 6.858 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Value" "TestPoint" + (at 0 5.08 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Footprint" "" + (at 5.08 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Datasheet" "~" + (at 5.08 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Description" "test point" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_keywords" "test point tp" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_fp_filters" "Pin* Test*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(pin_numbers + (hide yes) + ) +(pin_names + (offset 0.762) + (hide yes) + ) +(exclude_from_sim no) +(in_bom yes) +(on_board yes) +(symbol "TestPoint_0_1" + (circle + (center 0 3.302) + (radius 0.762) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + ) +(symbol "TestPoint_1_1" + (pin passive line + (at 0 0 90) + (length 2.54) + (name "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) +(embedded_fonts no) +) +(symbol "Connector:USB_C_Receptacle_USB2.0_16P" +(property "Reference" "J" + (at 0 22.225 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Value" "USB_C_Receptacle_USB2.0_16P" + (at 0 19.685 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) +(property "Footprint" "" + (at 3.81 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Datasheet" "https://www.usb.org/sites/default/files/documents/usb_type-c.zip" + (at 3.81 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "Description" "USB 2.0-only 16P Type-C Receptacle connector" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_keywords" "usb universal serial bus type-C USB2.0" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(property "ki_fp_filters" "USB*C*Receptacle*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) +(pin_names + (offset 1.016) + ) +(exclude_from_sim no) +(in_bom yes) +(on_board yes) +(symbol "USB_C_Receptacle_USB2.0_16P_0_0" + (rectangle + (start -0.254 -17.78) + (end 0.254 -16.764) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 15.494) + (end 9.144 14.986) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 10.414) + (end 9.144 9.906) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 7.874) + (end 9.144 7.366) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 2.794) + (end 9.144 2.286) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 0.254) + (end 9.144 -0.254) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 -2.286) + (end 9.144 -2.794) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 -4.826) + (end 9.144 -5.334) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 -12.446) + (end 9.144 -12.954) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (rectangle + (start 10.16 -14.986) + (end 9.144 -15.494) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + ) +(symbol "USB_C_Receptacle_USB2.0_16P_0_1" + (rectangle + (start -10.16 17.78) + (end 10.16 -17.78) + (stroke + (width 0.254) + (type default) + ) + (fill + (type background) + ) + ) + (polyline + (pts + (xy -8.89 -3.81) (xy -8.89 3.81) + ) + (stroke + (width 0.508) + (type default) + ) + (fill + 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"c1e3744a-1886-5121-a107-64b7bf761eb7") + ) + (wire + (pts + (xy 238.76 147.32) (xy 238.76 142.24) + ) + (stroke + (width 0) + (type default) + ) + (uuid "46172af2-9f2f-56a9-9e80-3ffc1b7ab84c") + ) + (wire + (pts + (xy 259.08 96.52) (xy 251.46 96.52) + ) + (stroke + (width 0) + (type default) + ) + (uuid "def4feeb-5b43-56b1-b980-7e83ab4d4b22") + ) + (wire + (pts + (xy 259.08 99.06) (xy 251.46 99.06) + ) + (stroke + (width 0) + (type default) + ) + (uuid "401ce679-ff7d-51bf-b5fc-bf3310d3bde5") + ) + (wire + (pts + (xy 259.08 101.6) (xy 251.46 101.6) + ) + (stroke + (width 0) + (type default) + ) + (uuid "20d05332-2c66-5472-9c17-3636d8bc1642") + ) + (wire + (pts + (xy 259.08 104.14) (xy 251.46 104.14) + ) + (stroke + (width 0) + (type default) + ) + (uuid "2cb8dbeb-4a8a-58df-b93f-18da8f1e6d58") + ) + (wire + (pts + (xy 259.08 106.68) (xy 251.46 106.68) + ) + (stroke + (width 0) + (type default) + ) + (uuid "bab59153-0ce8-5f7b-83ec-dd97327a5ddb") + ) + (wire + (pts + (xy 259.08 109.22) (xy 251.46 109.22) + ) + (stroke + (width 0) + (type default) + ) + (uuid "9898698a-f919-55ed-b637-f3ff022fc4c1") + ) + (text "USB-C, CH347F USB to JTAG / UART" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "849a40b7-3c58-5343-9ad1-f86cf7a640e8") + ) + (text "USB device (sink): CC1 and CC2 each 5.1k to GND -> 5 V from any USB-C host.\nF1: PTC 1.1 A hold / 2.2 A trip protects host and board against shorts.\nTVS SMF5.0A behind F1 clamps ESD on VBUS; a permanent overvoltage makes it conduct and trips F1.\nNo series resistors on D+/D- (built into CH347). ESD part < 2 pF (WCH).\nCH347F works without mode straps; used here: UART0 (TXD/RXD) + JTAG. UART1, modem lines,\nSPI and I2C are not connected (FPGA pin budget, see PINPLAN.md).\nVIO = 3.3 V = VCCIO of the FPGA banks the signals go to (JTAG: VCCIO8).\nNames as on the DE1, seen from the FPGA: UART_TXD = FPGA transmits, UART_RXD = FPGA receives." + (exclude_from_sim no) + (at 25.4 160.02 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "a2e94f3a-e63a-525c-8c3c-972c5542bc35") + ) + (text "JTAG pull resistors\n(ECP5 TN-02038)" + (exclude_from_sim no) + (at 208.28 132.08 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "6ca586ee-d27d-50c0-8abb-4dcbf3b11504") + ) + (text "not fitted (DNP)" + (exclude_from_sim no) + (at 254 116.84 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "49429b8b-33d9-5d5e-a2bc-05d710c2b3d2") + ) + (label "USB_D-" + (at 63.5 86.36 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "565a184c-8cd7-570a-9e92-e7942d93af6f") + ) + (label "USB_D+" + (at 63.5 91.44 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "b2440643-ccc1-536d-a4a8-5f270dfc0c3d") + ) + (label "USB_D+" + (at 33.02 134.62 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "69c245e8-3243-552c-a3f7-706de21d8701") + ) + (label "USB_D-" + (at 33.02 139.7 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "520de3f8-1461-5d47-8bc2-4ff98158a777") + ) + (label "USB_D+" + (at 124.46 101.6 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "f6fab609-209f-557e-82e9-3f89ce9471a7") + ) + (label "USB_D-" + (at 124.46 104.14 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "f00875c5-d2bc-5e35-b600-5a2a372d63c8") + ) + (global_label "UART_RXD" + (shape output) + (at 193.04 78.74 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "d98613be-68a4-5a00-a294-639ec64dc00b") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 193.04 78.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "UART_TXD" + (shape input) + (at 193.04 81.28 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "c9694548-3cce-5a5a-8969-432c708f2ca8") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 193.04 81.28 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "JTAG_TCK" + (shape output) + (at 193.04 114.3 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "a4291e03-0d4f-57c0-a7a3-d0bcdc91eacd") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 193.04 114.3 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "JTAG_TMS" + (shape output) + (at 193.04 116.84 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "8f7d5ae7-e75c-54c4-8866-27780242b4f1") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 193.04 116.84 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "JTAG_TDI" + (shape output) + (at 193.04 119.38 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "7cc57975-9b69-56e8-9afa-6dbc1661f43a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 193.04 119.38 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "JTAG_TDO" + (shape input) + (at 193.04 121.92 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "a788f50b-adbc-5129-8812-507c62f55bd2") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 193.04 121.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "JTAG_TDI" + (shape bidirectional) + (at 208.28 160.02 270) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "c7c854ec-f04d-5594-96ca-06a3fe51fe53") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 208.28 160.02 270) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "JTAG_TMS" + (shape bidirectional) + (at 218.44 160.02 270) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "dc2d90cd-c714-51ae-9adf-0cf0782c7b6a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 218.44 160.02 270) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "JTAG_TDO" + (shape bidirectional) + (at 228.6 160.02 270) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "95fb88ce-ca19-59e1-812f-77068a058b18") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 228.6 160.02 270) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "JTAG_TCK" + (shape bidirectional) + (at 238.76 142.24 90) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "b1e93178-afca-5ac6-86e1-966502050b87") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 238.76 142.24 90) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "JTAG_TCK" + (shape bidirectional) + (at 251.46 99.06 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d8f8af33-107b-5b15-9df5-8289f11903aa") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 251.46 99.06 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "JTAG_TDI" + (shape bidirectional) + (at 251.46 101.6 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "7545146b-4015-5bdd-9cd3-241426a1204f") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 251.46 101.6 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "JTAG_TDO" + (shape bidirectional) + (at 251.46 104.14 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "49c3aa6f-1bcd-5e1b-b19d-be80bdd63eef") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 251.46 104.14 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "JTAG_TMS" + (shape bidirectional) + (at 251.46 106.68 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "33d2b8bd-8688-5fa4-8171-e3254129a633") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 251.46 106.68 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (symbol + (lib_id "Connector:USB_C_Receptacle_USB2.0_16P") + (at 40.64 88.9 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "419d83ce-7758-5199-b482-ac57279daea4") + (property "Reference" "J1" + (at 30.48 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "USB_C" + (at 30.48 66.04 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12" + (at 40.64 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "https://www.usb.org/sites/default/files/documents/usb_type-c.zip" + (at 40.64 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "USB 2.0-only 16P Type-C Receptacle connector" + (at 40.64 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C165948" + (at 40.64 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "TYPE-C-31-M-12" + (at 40.64 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "HRO" + (at 40.64 88.9 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "A1" + (uuid "dcaaee66-739a-5316-9b4f-6212b9a864c3") + ) + (pin "A12" + (uuid "d099b9b6-2190-5795-a0e6-0463e2f35561") + ) + (pin "A4" + (uuid "02b9d41b-f1e3-5803-bdb8-578cbcb08472") + ) + (pin "A5" + (uuid "0c1ffac6-0704-5397-bc30-50f6adb79b53") + ) + (pin "A6" + (uuid "d6694db4-6cac-5515-9400-7e4d0fbba33a") + ) + (pin "A7" + (uuid "c5e22d39-8328-5806-9fb3-6813d52b8ea6") + ) + (pin "A8" + (uuid "fb52637a-cf07-51f0-b613-aad0e11a06f4") + ) + (pin "A9" + (uuid "68758455-c4ef-56d5-999d-be9465be415f") + ) + (pin "B1" + (uuid "b1c4f59e-de68-54c9-bd2b-311a468ef05a") + ) + (pin "B12" + (uuid "36df4dc2-37af-500a-b773-a49cb42ee703") + ) + (pin "B4" + (uuid "000e41dd-4e1d-53a3-82f4-fa71d3d8ba6f") + ) + (pin "B5" + (uuid "f63cb20a-0c28-526a-9bd2-ae80a3e2b3ba") + ) + (pin "B6" + (uuid "8d4b5d4a-7278-527a-9a64-c044008ec5fd") + ) + (pin "B7" + (uuid "e3d6a412-3f6a-5ac1-8e72-44bb83444d23") + ) + (pin "B8" + (uuid "f675cffb-1715-59f7-a729-b96381eb6389") + ) + (pin "B9" + (uuid "b32788b8-603d-5ca0-9f07-31a84c01b964") + ) + (pin "S1" + (uuid "90cbf64e-6cd3-54c6-a6a1-1b0b63357370") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/758d99eb-cd1e-58ec-83c7-9d724543d666" + (reference "J1") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 40.64 111.76 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "470481e5-7da6-5b52-85fc-4fbc4586dd3c") + (property "Reference" "#PWR24" + (at 40.64 118.11 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 38.735 116.205 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 40.64 111.76 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 40.64 111.76 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 40.64 111.76 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "9713b5df-a190-5880-afcf-03634717c5e3") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/758d99eb-cd1e-58ec-83c7-9d724543d666" + (reference "#PWR24") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:GND") + (at 33.02 111.76 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "b3a406e4-12ef-5c96-be8a-281584a06ad5") + (property "Reference" "#PWR25" + (at 33.02 118.11 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "GND" + (at 31.115 116.205 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 33.02 111.76 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 33.02 111.76 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Power symbol creates a global label with name \"GND\" , ground" + (at 33.02 111.76 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "d58e8ced-f208-5346-9291-19d377b6a9f2") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/758d99eb-cd1e-58ec-83c7-9d724543d666" + (reference "#PWR25") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:Polyfuse") + (at 68.58 73.66 90) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "392d4207-7ce3-554f-a3fd-d2c46ae5988b") + (property "Reference" "F1" + (at 68.58 68.58 90) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "1.1A" + (at 68.58 71.12 90) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "Fuse:Fuse_1206_3216Metric" + (at 68.58 73.66 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 68.58 73.66 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Resettable fuse, polymeric positive temperature coefficient" + (at 68.58 73.66 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "LCSC" "C269119" + (at 68.58 73.66 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "MPN" "SMD1206B110TFT" + (at 68.58 73.66 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Manufacturer" "Brightking" + (at 68.58 73.66 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid 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73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "d391d02f-1d24-5b27-b731-334182dd2f14") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/758d99eb-cd1e-58ec-83c7-9d724543d666" + (reference "TP1") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:PWR_FLAG") + (at 83.82 73.66 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "c1cc8dc1-690c-5d15-bca1-dd2a63df3dd0") + (property "Reference" "#FLG26" + (at 83.82 71.755 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "PWR_FLAG" + (at 81.28 68.58 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 83.82 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 83.82 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Special symbol for telling ERC where power comes from" + (at 83.82 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "2110d4ce-3298-59e1-8a61-cd8a222980df") + ) + (instances + (project "eboard" + (path "/7f75c49a-47aa-5b8b-918c-039c2c9bf06d/758d99eb-cd1e-58ec-83c7-9d724543d666" + (reference "#FLG26") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "power:+5V") + (at 93.98 73.66 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (uuid "84c3f1c0-3121-5594-8847-bf002a3bc276") + (property "Reference" "#PWR27" + (at 93.98 77.47 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + (property "Value" "+5V" + (at 92.075 69.215 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "" + (at 93.98 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 93.98 73.66 0) + (effects + (font + (size 1.27 1.27) + ) + (hide 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"0a8d1573-afbe-529b-a2bd-aa46a488960b") + ) + (wire + (pts + (xy 335.28 215.9) (xy 337.82 215.9) + ) + (stroke + (width 0) + (type default) + ) + (uuid "c6b8d11b-5284-5e9b-a733-9159f22036a2") + ) + (wire + (pts + (xy 335.28 220.98) (xy 337.82 220.98) + ) + (stroke + (width 0) + (type default) + ) + (uuid "5873b1c3-26e7-5846-82ed-7864b4dc0245") + ) + (wire + (pts + (xy 360.68 218.44) (xy 359.41 218.44) + ) + (stroke + (width 0) + (type default) + ) + (uuid "73cc597a-9068-51cd-a6d6-99434b72c08b") + ) + (wire + (pts + (xy 351.79 218.44) (xy 346.71 218.44) + ) + (stroke + (width 0) + (type default) + ) + (uuid "10b64378-b14f-58f4-9545-33bfabd25c1e") + ) + (wire + (pts + (xy 370.84 215.9) (xy 373.38 215.9) + ) + (stroke + (width 0) + (type default) + ) + (uuid "20b303b6-7bb8-52ee-992b-13165e07f2ea") + ) + (wire + (pts + (xy 370.84 220.98) (xy 373.38 220.98) + ) + (stroke + (width 0) + (type default) + ) + (uuid "fe5713e8-79f7-532d-9037-3e6f1b27fe0e") + ) + (text "KEY[3:0]: high when not pressed, low when pressed (as on the DE1).\nDebounced: button charges 100 nF via 1k, 47k discharges it (~5 ms),\n74HC14 Schmitt trigger inverts. Usable as clock input in lab designs." + (exclude_from_sim no) + (at 30.48 38.1 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "ff8231fe-33fa-5f8c-8610-28bbec589337") + ) + (text "LEDR[9:0], LEDG[5:0]: active high (as on the DE1).\nRed KT-0603R 1k (~1.3 mA), yellow-green XL-1608SYGC 470R (~2.3 mA)." + (exclude_from_sim no) + (at 154.94 38.1 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "efb460eb-4c55-5d1c-87a7-35787ad40db2") + ) + (text "HEX0" + (exclude_from_sim no) + (at 365.76 124.46 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "8b9702f4-6d0c-5d96-b47b-362a7293910b") + ) + (text "HEX1" + (exclude_from_sim no) + (at 287.02 124.46 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "68f6349c-9718-5f3a-b0d7-ae6029d41131") + ) + (text "HEX2" + (exclude_from_sim no) + (at 365.76 43.18 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "2d6ad154-8f42-5e67-a8b2-076f6576ffc6") + ) + (text "HEX3" + (exclude_from_sim no) + (at 287.02 43.18 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "c36b5a33-70d4-5f17-8bce-bdf76d1614a7") + ) + (text "HEX0[6:0] ... HEX3[6:0]: segment 0 = a ... 6 = g, active low (as on the DE1).\nCommon anode on 3.3 V, 330R per segment (~4 mA). Decimal point not connected." + (exclude_from_sim no) + (at 256.54 38.1 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "4c387c44-6f89-521f-88ae-3de3f35d0552") + ) + (text "SW[9:0]: vertical slide switches ROCPU SS-12D07-5 (C&K OS102011 footprint; C&K OS102011MS2QN1 fits too),\nthrough hole, not debounced (as on the DE1).\n1k series resistor protects the FPGA pin if it is driven as an output by mistake." + (exclude_from_sim no) + (at 30.48 198.12 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "018a5c20-2fee-53a4-b52a-f6f998933de5") + ) + (text "User I/O (DE1 compatible): SW, KEY, LEDR, LEDG, HEX" + (exclude_from_sim no) + (at 25.4 20.32 0) + (effects + (font + (size 2.54 2.54) + (bold yes) + ) + (justify left top) + ) + (uuid "ada59bf2-42f6-5b54-b1bc-a270f54f352c") + ) + (text "Net names = DE1 port names, see kicad/README.md. FPGA banks 3, 6 and 8 (PINPLAN.md)." + (exclude_from_sim no) + (at 25.4 27.94 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "b8f8ffa0-64e1-5557-abb9-a54c6131d7d8") + ) + (global_label "KEY0" + (shape output) + (at 115.57 55.88 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "cca541c0-225c-51ef-aae9-ca389d822300") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 115.57 55.88 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "KEY1" + (shape output) + (at 115.57 78.74 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "98b61b25-ae2c-53e5-8f06-c8200b1479af") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 115.57 78.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "KEY2" + (shape output) + (at 115.57 101.6 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "8ead5286-0346-56b8-bdfc-727db78e389e") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 115.57 101.6 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "KEY3" + (shape output) + (at 115.57 124.46 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "398efb4e-13cd-56d5-9971-d229b2c410ec") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 115.57 124.46 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + (hide yes) + ) + ) + ) + (global_label "LEDR0" + (shape input) + (at 163.83 50.8 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "b3eae2fd-1227-5d26-9f43-d124658cd247") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 50.8 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR1" + (shape input) + (at 163.83 58.42 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "29a10885-f14b-546a-b18a-cfe947801dd8") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 58.42 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR2" + (shape input) + (at 163.83 66.04 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "0401bc4d-4fd9-5899-9626-70772f920494") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 66.04 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR3" + (shape input) + (at 163.83 73.66 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "a4c457dd-8d4b-5e98-893e-8c29c0e79ba8") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 73.66 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR4" + (shape input) + (at 163.83 81.28 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "bf5c852b-3ce2-5eba-bd67-93722b76ff11") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 81.28 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR5" + (shape input) + (at 163.83 88.9 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "e7ec958d-d028-5ff1-ba11-622780731006") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 88.9 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR6" + (shape input) + (at 163.83 96.52 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "9050e756-3fe7-5932-bcba-36338fac5915") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 96.52 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR7" + (shape input) + (at 163.83 104.14 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2a608b28-ab69-54b8-8806-988510880bf1") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 104.14 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR8" + (shape input) + (at 163.83 111.76 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "44b3cacb-7be2-5820-befa-b2fc92b321da") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 111.76 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDR9" + (shape input) + (at 163.83 119.38 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "0d9ecf95-019d-5db1-b3f9-5c30bc1e3ad9") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 119.38 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDG0" + (shape input) + (at 163.83 132.08 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "c8422d35-09e3-50ae-a3b7-dfc2235c2016") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 132.08 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDG1" + (shape input) + (at 163.83 139.7 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "30c9a4bc-236d-502e-9b10-61b86493c973") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 139.7 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDG2" + (shape input) + (at 163.83 147.32 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2b27eb4b-9a8d-5386-9149-d6c44f96b5ea") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 147.32 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDG3" + (shape input) + (at 163.83 154.94 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "03be7e66-3029-52ca-83ee-f2d7cef29664") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 154.94 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDG4" + (shape input) + (at 163.83 162.56 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "d82d20fb-c3cd-50de-ad6d-b7564ce7314d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 162.56 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "LEDG5" + (shape input) + (at 163.83 170.18 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "a90f3305-38bb-5e18-91f7-bab5cc65f7d5") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 163.83 170.18 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (global_label "HEX0_0" + (shape input) + (at 339.09 132.08 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "5f2f8b62-e498-598c-bf01-d89006f305c6") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 132.08 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_A" + (at 356.87 132.08 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "44bcd94a-390b-5279-a2fd-8275d1ad2c5c") + ) + (global_label "HEX0_1" + (shape input) + (at 339.09 139.7 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "6bbe5927-d35e-5b76-907d-f38836917113") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 139.7 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_B" + (at 356.87 139.7 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "2d6ef5cb-ac6e-591f-87cd-b3f58f78f265") + ) + (global_label "HEX0_2" + (shape input) + (at 339.09 147.32 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "8ccee419-52ec-5663-966a-69641afcc85d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 147.32 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_C" + (at 356.87 147.32 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "3a68e0ea-6e42-5fa5-874d-a90f028555b3") + ) + (global_label "HEX0_3" + (shape input) + (at 339.09 154.94 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "00ebfd5c-ebf6-568f-98aa-41466a089e1d") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 154.94 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_D" + (at 356.87 154.94 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "5df47cbc-1187-5fe7-b96a-c00c77025890") + ) + (global_label "HEX0_4" + (shape input) + (at 339.09 162.56 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "95cb2bc5-825b-51ce-92ba-7ad932029563") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 162.56 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_E" + (at 356.87 162.56 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "2357562c-b1aa-5a73-ba8f-2d115081fb6d") + ) + (global_label "HEX0_5" + (shape input) + (at 339.09 170.18 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "4f057bcf-ead3-5d2c-96bc-07c8f6fc5239") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 170.18 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_F" + (at 356.87 170.18 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "3f097a07-0cb9-517c-8963-204c6e5be548") + ) + (global_label "HEX0_6" + (shape input) + (at 339.09 177.8 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "f621f814-9d14-53f6-9627-7fb08806857c") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 339.09 177.8 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H0_G" + (at 356.87 177.8 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "f63f9796-8e08-5a21-b0da-a4426060d96e") + ) + (label "H0_A" + (at 375.92 152.4 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "ac196341-6c1a-5838-b00a-a8290a821f1b") + ) + (label "H0_B" + (at 375.92 154.94 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "7d210e3c-d51e-52bc-b588-5490c40fbe68") + ) + (label "H0_C" + (at 375.92 157.48 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "43277ae3-6031-5ccf-b467-bb5df16e0d7f") + ) + (label "H0_D" + (at 375.92 160.02 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "8f81acc2-bb48-5430-bd6b-bcad48714c47") + ) + (label "H0_E" + (at 375.92 162.56 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "da71bf2f-5430-5702-ac99-a3b5e1f9c123") + ) + (label "H0_F" + (at 375.92 165.1 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "f8ff69ef-3895-5300-87b1-5fd13dadb05f") + ) + (label "H0_G" + (at 375.92 167.64 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right bottom) + ) + (uuid "72f61362-e34e-5ea1-95e0-906305123e71") + ) + (global_label "HEX1_0" + (shape input) + (at 260.35 132.08 180) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "2d5da42b-9949-56fb-b875-9fa66e4ebc8a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 260.35 132.08 180) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + (hide yes) + ) + ) + ) + (label "H1_A" + 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