#### eboard pin plan (draft 4) #### Bank-level assignment of the board interfaces to the ECP5 LFE5U-25F/45F in caBGA256. All banks run at VCCIO = 3.3 V. The ball-level assignment below is in the schematic (sheets `fpga_banks_*`, bank 8 in `fpga_config`); it is preliminary and may change within a bank during layout (BGA escape routing). ### Banks of the caBGA256 package ### Top view, ball A1 top left. Source: Lattice pinout CSVs FPGA-SC-02033 (25F) and FPGA-SC-02034 (45F); both are identical per bank. | Bank | Location | I/O | Notes | |------|--------------------------|-----|----------------------------------------------------| | 0 | top left (A-E, 2-8) | 24 | 12 A/B pairs, PCLKT0_0 A7, PCLKT0_1 C7 | | 1 | top right (A-E, 8-15) | 32 | 16 A/B pairs, PCLKT1_0 C8, PCLKT1_1 E8 | | 2 | right upper (B-K, 12-16) | 32 | true LVDS pairs, PCLKT2_0 K16, PCLKT2_1 J16 | | 3 | right lower (K-T, 11-16) | 32 | true LVDS pairs, PCLKT3_0 M16, PCLKT3_1 L16 | | 6 | left lower (K-T, 1-6) | 32 | true LVDS pairs, PCLKT6_0 M1, PCLKT6_1 L1 | | 7 | left upper (B-K, 1-5) | 32 | true LVDS pairs, PCLKT7_0 K1, PCLKT7_1 J1 | | 8 | bottom (M-T, 6-9) | 13 | configuration bank; 5 used by the quad SPI flash, 8 free | 197 user I/O in total, 192 without the flash pins. Balls B1 B2 A2 B3 B14 A15 B15 B16 are PLL inputs on the 45F only and plain I/O on the 25F: no clocks on these balls. ### Interfaces ### | Interface | Pins | Notes | |-------------------------------|------|----------------------------------------------------| | `CLOCK_50` | 1 | 50 MHz oscillator | | SDRAM 32 MB, x16 W9825G6KH-6 (`DRAM_*`) | 39 | DQ 16, ADDR 13, BA 2, DQM 2, CLK, CKE, CS, RAS, CAS, WE | | Ethernet RTL8211F, RGMII (`ENET_*`) | 16 | GTX_CLK TX_EN TX_DATA0-3, RX_CLK RX_DV RX_DATA0-3, MDC, MDIO, RST_N, INT_N | | HDMI out (`HDMI_*`) | 8 | 4 TMDS pairs (LVCMOS33D, as ULX3S), 22 nF AC coupling; no DDC/HPD | | CH347 UART | 2 | `UART_TXD`, `UART_RXD` | | `SW[9:0]`, `KEY[3:0]` | 14 | | | `LEDR[9:0]`, `LEDG[5:0]` | 16 | | | `HEX0[6:0]` ... `HEX3[6:0]` | 28 | segments driven directly, as on the DE1 | | `GPIO_0[31:0]` | 32 | DE1 40 pin header; pins 37-40 fixed for the THDB-ADA; Pmod A/B share 16 of these pins | | `GPIO_1[35:0]` | 36 | DE1 40 pin header at the board edge, fully DE1 compatible | | **Total** | **192** | of 192 available | The SPI flash keeps all four data lines (quad SPI), e.g. for running code from the flash (execute in place, as on the Raspberry Pi Pico). Dropped to make it fit: UART1 and the modem lines of the CH347, HDMI DDC/HPD, and `GPIO_0[35:32]` as FPGA pins (see below). The Pmods are wired in parallel to `GPIO_0` and cannot be used together with a card on `GPIO_0`. ### `GPIO_0`: made for the THDB-ADA ### `GPIO_0` is fully DE1 compatible except for header pins 37-40, which are fixed on the board for the THDB-ADA instead of going to the FPGA: | Header pin | DE1 name | THDB-ADA signal | On eboard | Effect on the card | |------------|--------------|-----------------|--------------------------|----------------------------------| | 37 | `GPIO_0[32]` | POWER_ON | 10k pull-up to 3.3 V | ADC and clock buffer on | | 38 | `GPIO_0[33]` | ADC_OEB | 10k pull-down | ADC channel B outputs enabled | | 39 | `GPIO_0[34]` | (not used) | not connected | | | 40 | `GPIO_0[35]` | ADC_OEA | 10k pull-down | ADC channel A outputs enabled | On the THDB-ADA (schematic ada_v11), POWER_ON drives the AD9248 PDWN_A/B and the clock buffer enables through an inverter (74HC1G04); its 2k pull-up R59 is not fitted, and OEA/OEB go directly to the AD9248. So the card needs these levels from the board. ADC power-down and output tri-state are no longer controlled by the FPGA. Other DE1 cards work on `GPIO_0` if they do not use header pins 37-40. ### Assignment ### | Bank | Assignment | Used | |------|----------------------------------------------------------------|------| | 0 | Ethernet RGMII + MDC/MDIO + RESET/INT (16), HDMI (8) | 24 | | 1 | `GPIO_0[31:0]` (32), incl. the Pmod pins | 32 | | 2 | `GPIO_1[31:0]` (32) | 32 | | 3 | `GPIO_1[35:32]` (4), `HEX0`-`HEX2`, `HEX3[4:0]` (26), `UART_TXD/RXD` (2) | 32 | | 6 | `CLOCK_50` (M1), SDRAM (7), `SW` (10), `KEY` (4), `LEDR` (10) | 32 | | 7 | SDRAM (32): DQ[15:0], DQM[1:0], ADDR, CLK | 32 | | 8 | `LEDG` (6), `HEX3[6:5]` (2) | 8 | Rules for the ball assignment: - `CLOCK_50` on M1 (PCLKT6_0). - Ethernet RXC on a PCLK input of bank 0 (A7 = PCLKT0_0); RXD0-3 and RX_CTL close to it. TXC is generated with an ODDR, any pin. - HDMI: each TMDS pair on an A/B ball pair of bank 0 (true + complement). - SDRAM: DQ and DQM together in bank 7, short and equal-length traces. - DE1 header pins 1 and 3 (`GPIO_x[0]`, `GPIO_x[2]`) on PCLK inputs: `GPIO_1` on K16 / J16 (bank 2), `GPIO_0` on C8 / E8 (bank 1). On the THDB-ADA these are the clock inputs `SMA_DAC4` and `OSC_SMA_ADC4`. - The 8 PLL-only balls of the 45F carry data or user I/O, never clocks. DE1 header pinout (both headers): pins 1-10 = `GPIO_x[0..9]`, 11 = 5 V, 12 = GND, 13-28 = `GPIO_x[10..25]`, 29 = 3.3 V, 30 = GND, 31-40 = `GPIO_x[26..35]`. **On eboard pin 11 carries 3.3 V instead of 5 V**: there is no 5 V on the headers (the THDB-ADA does not use pin 11). The 68 FPGA lines of both headers are connected directly (as on ULX3S) and protected by 17 TPD4E05U06 ESD arrays (4 lines each, 0.3 pF) at the headers. Pmod A (GPIO_0_0..7) and Pmod B (GPIO_0_8..15): 2x6 right angle sockets. ### THDB-ADA on `GPIO_0` + `GPIO_1` ### The THDB-ADA (Terasic AD/DA card: AD9248 dual 14 bit ADC, AD9767 dual 14 bit DAC) uses 35 of the 36 I/O of each header: - `GPIO_0` (J7): ADC A/B data, OTRA/OTRB, ADC clocks A/B, OEA/OEB, POWER_ON. - `GPIO_1` (J8): DAC A/B data, WRTA/WRTB, DAC clocks A/B, DAC_MODE, clock inputs `SMA_DAC4` (pin 1) and `OSC_SMA_ADC4` (pin 3). Sources: THDB-ADA User Manual (Terasic, October 2015), section 3.3; THDB-ADA schematic ada_v11. ### Mechanics of the GPIO headers ### Coordinates in mm, origin at the bottom left board corner, y up, as in the DE1 outline drawing (DE1 CD-ROM, `DE1_schematics/DE1_outline.pdf`). DE1 board: 152.146 x 152.146 mm, mounting holes 3 mm at (4.191, 4.191), (4.191, 32.385), (4.191, 147.955), (147.955, 4.191), (147.955, 32.385), (147.955, 147.955). **eboard uses the same outline and mounting holes.** | Header | Pin 1 (square pad) | Orientation | |------------------|--------------------|-----------------------------------------------| | JP1 = `GPIO_0` | (125.603, 118.745) | vertical, pin 2 at x + 2.54, pins 39/40 at y = 70.485 | | JP2 = `GPIO_1` | (145.923, 118.745) | same; 20.32 mm (0.8") right of JP1, 6.22 mm from the right edge | Both are 2x20 box headers, 2.54 mm pitch, keying notch on the left side. THDB-ADA outline, derived from the photo in Figure 1-2 of the THDB-ADA user manual (rotated by 180 degrees into the mounted position, scale from the header pitch, accuracy about +-1 mm). The card is 87.6 x 76.1 mm and sticks out 49 mm beyond the right board edge: | Part of the card | x | y | |-------------------------------------|---------------|---------------| | strip left of and under JP1 | 113.7 - 132.3 | 57.1 - 133.2 | | middle part (both headers) | 132.3 - 182.8 | 66.3 - 123.2 | | outer tabs (outside the board) | 182.8 - 201.3 | 57.1 - 133.2 | | mounting holes over the board | (119.3, 60.4), (118.7, 129.0) | | Keep-out on eboard under the plugged-in card (2 mm margin), polygon: (111.7, 55.1) - (134.3, 55.1) - (134.3, 64.3) - (152.1, 64.3) - (152.1, 125.2) - (134.3, 125.2) - (134.3, 135.2) - (111.7, 135.2). Inside: only low SMD parts (no connectors, buttons, electrolytic capacitors, displays), and keep about 8 mm around the two card mounting holes free for spacers. To be checked against a real card (outline, hole positions and the stack height above the board) before the layout is fixed. ### Board placement (top view) ### ``` +-----------------------------------------------------------------+ | USB-C HDMI RJ45 Pmod A Pmod B | | CH347 RTL8211F | | bank 0 bank 1 GPIO_0 GPIO_1 | SDRAM +---------------------+ :: :: | bank 7 | | bank 2 :: :: | | ECP5 BG256 | :: :: | bank 6 | | bank 3 :: :: | +---------------------+ | | 50 MHz bank 8: flash | | | | LEDR[9:0] LEDG[5:0] HEX3 HEX2 HEX1 HEX0 | | SW[9:0] KEY[3:0] | +-----------------------------------------------------------------+ ``` Test points: two scope ground loops (Keystone 5011, TP6/TP7, GPIO sheet) for the students' crocodile clips, one next to the GPIO headers and one next to the Pmods, both outside the THDB-ADA keep-out. Bring-up and production test use round 1.5 mm top-layer pads (no part): +5V, +3V3, +2V5, +1V1, 4x GND, VBUS, ETH_1V0, CLOCK_50, UART_TXD/RXD, FPGA_PROGRAMN/INITN/DONE. The connectors sit on the top edge, the user I/O on the bottom edge and both GPIO headers on the right edge (as on the DE1), with `GPIO_1` at the board edge. The SDRAM sits left of the FPGA. ### Ball assignment (preliminary) ### GPIO pairs: header neighbours `GPIO_x[2k]` / `GPIO_x[2k+1]` sit on the true / complement ball of one pair (true LVDS pairs in bank 2 and 3), so adjacent header pins can be used as a differential pair. | Bank | Net and ball | |------|--------------| | 0 | `ENET_GTX_CLK` D7, `ENET_INT_N` C5, `ENET_MDC` D4, `ENET_MDIO` E4, `ENET_RST_N` B5, `ENET_RX_CLK` A7, `ENET_RX_DATA0` B7, `ENET_RX_DATA1` C7, `ENET_RX_DATA2` B6, `ENET_RX_DATA3` C6, `ENET_RX_DV` A8, `ENET_TX_DATA0` D6, `ENET_TX_DATA1` E6, `ENET_TX_DATA2` D5, `ENET_TX_DATA3` E5, `ENET_TX_EN` E7, `HDMI_CLK_N` A6, `HDMI_CLK_P` A5, `HDMI_D0_N` B4, `HDMI_D0_P` C4, `HDMI_D1_N` A4, `HDMI_D1_P` A3, `HDMI_D2_N` B3, `HDMI_D2_P` A2 | | 1 | `GPIO_0_0` C8, `GPIO_0_1` B8, `GPIO_0_2` E8, `GPIO_0_3` D8, `GPIO_0_4` B9, `GPIO_0_5` C9, `GPIO_0_6` D9, `GPIO_0_7` E9, `GPIO_0_8` A9, `GPIO_0_9` A10, `GPIO_0_10` B10, `GPIO_0_11` C10, `GPIO_0_12` D10, `GPIO_0_13` E10, `GPIO_0_14` B11, `GPIO_0_15` C11, `GPIO_0_16` D11, `GPIO_0_17` E11, `GPIO_0_18` A11, `GPIO_0_19` A12, `GPIO_0_20` B12, `GPIO_0_21` C12, `GPIO_0_22` D12, `GPIO_0_23` E12, `GPIO_0_24` B13, `GPIO_0_25` C13, `GPIO_0_26` D13, `GPIO_0_27` E13, `GPIO_0_28` A13, `GPIO_0_29` A14, `GPIO_0_30` B14, `GPIO_0_31` A15 | | 2 | `GPIO_1_0` K16, `GPIO_1_1` K15, `GPIO_1_2` J16, `GPIO_1_3` J15, `GPIO_1_4` J14, `GPIO_1_5` K14, `GPIO_1_6` G16, `GPIO_1_7` H15, `GPIO_1_8` J13, `GPIO_1_9` J12, `GPIO_1_10` H12, `GPIO_1_11` H13, `GPIO_1_12` G14, `GPIO_1_13` H14, `GPIO_1_14` F16, `GPIO_1_15` G15, `GPIO_1_16` F15, `GPIO_1_17` E16, `GPIO_1_18` G12, `GPIO_1_19` G13, `GPIO_1_20` F13, `GPIO_1_21` F12, `GPIO_1_22` D16, `GPIO_1_23` E15, `GPIO_1_24` E14, `GPIO_1_25` F14, `GPIO_1_26` C16, `GPIO_1_27` C15, `GPIO_1_28` C14, `GPIO_1_29` D14, `GPIO_1_30` B16, `GPIO_1_31` B15 | | 3 | `GPIO_1_32` L16, `GPIO_1_33` L15, `GPIO_1_34` M16, `GPIO_1_35` M15, `HEX0_0` L13, `HEX0_1` L12, `HEX0_2` L14, `HEX0_3` M14, `HEX0_4` N16, `HEX0_5` P15, `HEX0_6` M13, `HEX1_0` N14, `HEX1_1` P16, `HEX1_2` R16, `HEX1_3` N13, `HEX1_4` T15, `HEX1_5` R15, `HEX1_6` P14, `HEX2_0` P13, `HEX2_1` T14, `HEX2_2` R13, `HEX2_3` R14, `HEX2_4` M12, `HEX2_5` N12, `HEX2_6` R12, `HEX3_0` T13, `HEX3_1` M11, `HEX3_2` P12, `HEX3_3` N11, `HEX3_4` P11, `UART_RXD` K13, `UART_TXD` K12 | | 6 | `CLOCK_50` M1, `DRAM_BA_0` K4, `DRAM_BA_1` K5, `DRAM_CAS_N` L1, `DRAM_CKE` M2, `DRAM_CS_N` L4, `DRAM_RAS_N` L5, `DRAM_WE_N` L2, `KEY0` M6, `KEY1` N6, `KEY2` P6, `KEY3` P5, `LEDR0` L3, `LEDR1` M3, `LEDR2` N1, `LEDR3` P2, `LEDR4` M4, `LEDR5` P1, `LEDR6` R1, `LEDR7` N3, `LEDR8` N4, `LEDR9` R2, `SW0` P3, `SW1` T2, `SW2` P4, `SW3` R4, `SW4` R3, `SW5` T3, `SW6` R5, `SW7` M5, `SW8` T4, `SW9` N5 | | 7 | `DRAM_ADDR0` H3, `DRAM_ADDR1` H5, `DRAM_ADDR2` J4, `DRAM_ADDR3` H4, `DRAM_ADDR4` J5, `DRAM_ADDR5` G1, `DRAM_ADDR6` J3, `DRAM_ADDR7` H2, `DRAM_ADDR8` K3, `DRAM_ADDR9` J1, `DRAM_ADDR10` K1, `DRAM_ADDR11` J2, `DRAM_ADDR12` K2, `DRAM_CLK` G2, `DRAM_DQ0` B1, `DRAM_DQ1` B2, `DRAM_DQ2` C3, `DRAM_DQ3` D3, `DRAM_DQ4` C1, `DRAM_DQ5` E3, `DRAM_DQ6` C2, `DRAM_DQ7` F3, `DRAM_DQ8` F4, `DRAM_DQ9` E2, `DRAM_DQ10` F5, `DRAM_DQ11` G5, `DRAM_DQ12` F2, `DRAM_DQ13` G4, `DRAM_DQ14` E1, `DRAM_DQ15` F1, `DRAM_LDQM` D1, `DRAM_UDQM` G3 | | 8 | `HEX3_5` M8, `HEX3_6` M9, `LEDG0` T6, `LEDG1` R7, `LEDG2` R6, `LEDG3` P7, `LEDG4` R8, `LEDG5` P8 | ### Open points ### - Measure a real THDB-ADA: outline, mounting holes, stack height (the keep-out above is derived from a photo). - Layer count for the BGA escape (0.8 mm pitch): ULX3S routes the larger caBGA381 on 4 layers, so 4 layers should work; to be confirmed in layout. - No spare FPGA pin. If one is needed later: drive ADC_CLK_A and ADC_CLK_B (`GPIO_0` pins 19/21) from one FPGA pin, as in the current lab designs.