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	(text "RGMII series resistors 22R:\nTX (ENET_GTX_CLK ... ENET_TX_DATA3) close to the FPGA,\nRX (ENET_RX_CLK ... ENET_RX_DATA3) close to the PHY."
		(exclude_from_sim no)
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	(text "PHYAD0 = 1"
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	(text "PHYAD1 = 0"
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	(text "PHYAD2 = 0"
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	(text "PLLOFF = 0"
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	(text "TXDLY = 1"
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	(text "RXDLY = 1"
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	(text "CFG_EXT = 1"
		(exclude_from_sim no)
		(at 121.92 231.14 0)
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	(text "CFG_LDO0 = 0"
		(exclude_from_sim no)
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	(text "CFG_LDO1 = 0"
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		(uuid "3924ad87-6d6a-597c-811d-6c5174c115b1")
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	(text "Strap resistors (RTL8211F datasheet 7.8): PHY address 1, 2 ns TXC and RXC delay inside the PHY,\nRGMII I/O at 3.3 V from DVDD_RG (CFG_EXT = 1, CFG_LDO = 00), LED1/LED2 active high."
		(exclude_from_sim no)
		(at 30.48 182.88 0)
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		(uuid "202e9358-c6d3-59a3-81ca-1d84fcbdccf8")
	)
	(text "ENET_RST_N: 10k pull-down keeps the PHY in reset\nuntil the FPGA drives it high (>= 10 ms low,\nwait 50 ms before MDIO access)."
		(exclude_from_sim no)
		(at 172.72 233.68 0)
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		(uuid "943c4bb0-0d75-57f1-86e2-d1967d4a3131")
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	(text "DVDD33, DVDD_RG"
		(exclude_from_sim no)
		(at 241.3 41.91 0)
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		(uuid "2dcc55d5-c431-5ddf-8628-a707d7e28c5e")
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	(text "AVDD33 (pins 11, 40)"
		(exclude_from_sim no)
		(at 294.64 41.91 0)
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		(uuid "12a16bfd-062c-5e3a-950f-7e613fca8d82")
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	(text "Test pad: PHY 1.0 V"
		(exclude_from_sim no)
		(at 345.44 60.96 0)
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		(uuid "f57a51c3-e88d-595f-b7a3-c8e79fbe90b9")
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	(text "1.0 V core (DVDD10 pin 21, AVDD10 pins 3, 8, 38): only for the PHY.\nInductor Isat > 600 mA, X5R/X7R capacitors."
		(exclude_from_sim no)
		(at 236.22 96.52 0)
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		(uuid "968f64b3-07e5-5a71-9304-560e082f2956")
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	(text "RJ45 with 1000Base-T magnetics. Transformer centre tap via 100 nF to GND\n(voltage-mode PHY, no external MDI termination needed).\nLEDs: green = LED2 (1000 Mbit/s link/activity), yellow = LED1 (100 Mbit/s).\nShield ETH_SHIELD: 1M || 1 nF 2 kV to GND, keeps the 1500 V isolation of the magnetics\nwith shielded cables. Layout: own copper island under the jack shell, >= 2 mm gap to GND."
		(exclude_from_sim no)
		(at 294.64 198.12 0)
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	(text "Ethernet: RTL8211F gigabit PHY, RGMII to the FPGA bank 0"
		(exclude_from_sim no)
		(at 25.4 20.32 0)
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	(text "Net names as on the DE2-115 (ENET_*), seen from the FPGA. RXC (ENET_RX_CLK) goes to a PCLK pin (A7).\n3.3 V rise time must be >= 0.5 ms (TLV62569 soft start: 0.8 ms)."
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	(label "PHY_TXC"
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	(label "PHY_TXCTL"
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	(label "PHY_TXD0"
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	(label "PHY_TXD1"
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	(label "PHY_TXD2"
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	(label "PHY_TXD3"
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	(label "PHY_RXC"
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	(global_label "ENET_MDC"
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	(global_label "ENET_MDIO"
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