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219.71 139.7) ) (stroke (width 0) (type default) ) (uuid "867f4551-1632-546a-aa63-6e6404897e68") ) (wire (pts (xy 27.94 172.72) (xy 38.1 172.72) ) (stroke (width 0) (type default) ) (uuid "9acc2c5a-5f33-5ab7-98e5-c535e53fb6f0") ) (wire (pts (xy 38.1 172.72) (xy 50.8 172.72) ) (stroke (width 0) (type default) ) (uuid "cf79118d-25a1-5f7c-be29-902517f32529") ) (wire (pts (xy 50.8 172.72) (xy 63.5 172.72) ) (stroke (width 0) (type default) ) (uuid "af2d5476-2e2c-58fd-b0a2-1a7076012267") ) (wire (pts (xy 63.5 172.72) (xy 76.2 172.72) ) (stroke (width 0) (type default) ) (uuid "747621ee-4d32-5df7-a472-55d2be51c6b7") ) (wire (pts (xy 76.2 172.72) (xy 88.9 172.72) ) (stroke (width 0) (type default) ) (uuid "b3b43aa3-c8e4-5d2c-a68c-7f556558668c") ) (wire (pts (xy 88.9 172.72) (xy 101.6 172.72) ) (stroke (width 0) (type default) ) (uuid "f9e45941-739b-5b93-b1fb-eaf5d6b582b8") ) (wire (pts (xy 101.6 172.72) (xy 114.3 172.72) ) (stroke (width 0) (type default) ) (uuid "80d5d893-e71d-5814-a0b6-917a130169e1") ) (wire (pts (xy 114.3 172.72) (xy 127 172.72) ) (stroke (width 0) (type default) ) (uuid "fae1197d-4d6c-5793-b5f7-29affb63d6da") ) (text "DRAM_CLK series resistor\nclose to the FPGA" (exclude_from_sim no) (at 200.66 127 0) (effects (font (size 1.27 1.27) ) (justify left top) ) (uuid "d5af7893-6cd3-512e-890c-7fe226c34963") ) (text "Decoupling: 10 uF bulk, 100 nF at each VDD (1, 14, 27) and VDDQ (3, 9, 43, 49) pin." (exclude_from_sim no) (at 27.94 163.83 0) (effects (font (size 1.27 1.27) ) (justify left top) ) (uuid "6a5ef66a-e794-521d-9e8b-b8bc642590f4") ) (text "SDRAM 32 MB: Winbond W9825G6KH-6 (JLCPCB C62246), 16 bit, 166 MHz" (exclude_from_sim no) (at 25.4 20.32 0) (effects (font (size 2.54 2.54) (bold yes) ) (justify left top) ) (uuid "8c624df5-32dc-5eb9-80fa-1cbebd3d5615") ) (text "Pin compatible with Micron MT48LC16M16A2TG (KiCad symbol, as on ULX3S). Net names as on the DE1\n(DRAM_*), plus DRAM_ADDR12 for 32 MB. FPGA banks 7 + 6 (PINPLAN.md); short traces, no series\nresistors on data/address (as on ULX3S)." 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