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No part:\nnot in the BOM, not in the placement file. Further test pads on their sheets: VBUS (USB),\nFPGA_PROGRAMN / FPGA_INITN / FPGA_DONE (FPGA config), ETH_1V0 (Ethernet).\nJTAG: the 1x6 header footprint J2 (USB sheet, not fitted) serves as test access.\nScope ground loops for the lab (Keystone 5011): GPIO sheet." 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