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<updated>2025-03-18T13:07:33Z</updated>
<entry>
<title>add de1_dac</title>
<updated>2025-03-18T13:07:33Z</updated>
<author>
<name>Friedrich Beckmann</name>
<email>friedrich.beckmann@hs-augsburg.de</email>
</author>
<published>2025-03-18T13:07:33Z</published>
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<entry>
<title>add de1_ledsw</title>
<updated>2025-03-18T13:06:38Z</updated>
<author>
<name>Friedrich Beckmann</name>
<email>friedrich.beckmann@hs-augsburg.de</email>
</author>
<published>2025-03-18T12:20:17Z</published>
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<entry>
<title>added de1_adc</title>
<updated>2023-04-17T14:14:44Z</updated>
<author>
<name>Friedrich Beckmann</name>
<email>friedrich.beckmann@hs-augsburg.de</email>
</author>
<published>2023-04-17T14:14:44Z</published>
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<entry>
<title>matlab: add dds phase model</title>
<updated>2023-03-29T04:51:35Z</updated>
<author>
<name>Friedrich Beckmann</name>
<email>friedrich.beckmann@gmx.de</email>
</author>
<published>2023-03-29T04:51:35Z</published>
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<id>urn:sha1:47ed98f08a7d0ee14bcde29036a77431cc358e40</id>
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</entry>
<entry>
<title>makefile.ghdl - now shows errors on command line</title>
<updated>2023-03-23T14:20:02Z</updated>
<author>
<name>Johann Faerber</name>
<email>johann.faerber@hs-augsburg.de</email>
</author>
<published>2023-03-23T14:20:02Z</published>
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<entry>
<title>added de1_sine sinewave generator for ADC/DAC board</title>
<updated>2023-03-15T21:30:08Z</updated>
<author>
<name>Friedrich Beckmann</name>
<email>friedrich.beckmann@hs-augsburg.de</email>
</author>
<published>2023-03-15T21:30:08Z</published>
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<id>urn:sha1:df418208aa0570a99f6ab6657d54ee65d6162168</id>
<content type='text'>
I added a sinewave generator based on DDS in VHDL to
generate a sinewave with the ADC/DAC board. This can
be used to demonstrate the Aliasing Lowpass filter.
</content>
</entry>
<entry>
<title>renamed makefile to makefile.modelsim, added makefile.ghdl and symbolic link</title>
<updated>2023-03-12T13:35:11Z</updated>
<author>
<name>Johann Faerber</name>
<email>johann.faerber@hs-augsburg.de</email>
</author>
<published>2023-03-12T13:35:11Z</published>
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</content>
</entry>
<entry>
<title>Created stub for DDS test with ADDA-board using Simulink flow</title>
<updated>2022-06-15T15:31:01Z</updated>
<author>
<name>Matthias Kamuf</name>
<email>matthias.kamuf@hs-augsburg.de</email>
</author>
<published>2022-06-15T15:31:01Z</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>add / update de1_sta code</title>
<updated>2022-05-16T16:40:52Z</updated>
<author>
<name>Friedrich Beckmann</name>
<email>friedrich.beckmann@hs-augsburg.de</email>
</author>
<published>2022-05-16T16:40:52Z</published>
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<id>urn:sha1:fda13db347b69d24b7327a5b48cd2af7abfc6408</id>
<content type='text'>
I modified the de1_sta demo code and added a testbench.
</content>
</entry>
<entry>
<title>Added FIR design files for DE1 top level</title>
<updated>2022-05-16T14:46:04Z</updated>
<author>
<name>Matthias Kamuf</name>
<email>matthias.kamuf@hs-augsburg.de</email>
</author>
<published>2022-05-16T14:46:04Z</published>
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