beckmanf/mengcom.git/sim, branch masterUnnamed repository; edit this file 'description' to name the repository.
makefile.ghdl - now shows errors on command line2023-03-23T14:20:02+00:00Johann Faerberjohann.faerber@hs-augsburg.de2023-03-23T14:20:02+00:00acb927555f077ffc80bc38575537e9bf2a5b5793
added de1_sine sinewave generator for ADC/DAC board2023-03-15T21:30:08+00:00Friedrich Beckmannfriedrich.beckmann@hs-augsburg.de2023-03-15T21:30:08+00:00df418208aa0570a99f6ab6657d54ee65d6162168
I added a sinewave generator based on DDS in VHDL to
generate a sinewave with the ADC/DAC board. This can
be used to demonstrate the Aliasing Lowpass filter.
I added a sinewave generator based on DDS in VHDL to
generate a sinewave with the ADC/DAC board. This can
be used to demonstrate the Aliasing Lowpass filter.
renamed makefile to makefile.modelsim, added makefile.ghdl and symbolic link2023-03-12T13:35:11+00:00Johann Faerberjohann.faerber@hs-augsburg.de2023-03-12T13:35:11+00:000ace43acf8c1953289ae9ae3756d9f10949f060e
add / update de1_sta code2022-05-16T16:40:52+00:00Friedrich Beckmannfriedrich.beckmann@hs-augsburg.de2022-05-16T16:40:52+00:00fda13db347b69d24b7327a5b48cd2af7abfc6408
I modified the de1_sta demo code and added a testbench.
I modified the de1_sta demo code and added a testbench.
Added source files for simple FIR filter2022-05-04T12:56:11+00:00Matthias Kamufmatthias.kamuf@hs-augsburg.de2022-05-04T12:56:11+00:001d5a8634e3a54bbcd2e6ac3074e6c38f085feef0
removed sim/pwm and pnr/de1_pwm2022-03-13T15:07:05+00:00Johann Faerberjohann.faerber@hs-augsburg.de2022-03-13T15:07:05+00:0016fb5e54b5486e20facbd720b62f21521e3417cf