2 files changed, 48 insertions, 0 deletions
diff --git a/sim/binto7segment/makefile b/sim/binto7segment/makefile
new file mode 100644
index 0000000..2e21fe2
--- /dev/null
+++ b/sim/binto7segment/makefile
@@ -0,0 +1,31 @@
+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = binto7segment
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
diff --git a/sim/binto7segment/makefile.sources b/sim/binto7segment/makefile.sources
new file mode 100644
index 0000000..0b73c93
--- /dev/null
+++ b/sim/binto7segment/makefile.sources
@@ -0,0 +1,17 @@
+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/binto7segment_truthtable.vhd \
+
+# do not delete this line
+# -----------------------------------------------------------------------------
+\ No newline at end of file